HMC1126ACEZ-R7 datasheet(17/21 Pages) AD

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Data Sheet

HMC1126ACEZ

Rev. 0 | Page 17 of 21

BIASING THE HMC1126ACEZ WITH THE

HMC920LP5E

The HMC920LP5E (see Figure 58) is designed to provide active

bias control for enhancement mode and depletion mode

amplifiers, such as the HMC1126ACEZ. The HMC920LP5E

measures and regulates drain current to compensate for

temperature changes and part to part variations.

CONTROL

BLOCK

GATE

CONTROL

BANDGAP

DIGITAL

LDO

VDD1

CURALM

BGCAP

PORCAP

VDIGFB

VDIG

VDD1

TRGOUT

AGND

VNEGFB

VNEGIN

VGATEFB

VGATE

VDRAIN

DRAIN

LDO

NEGATIVE VOLTAGE

REGULATOR

PACKAGE

BASE

HMC920LP5E

Figure 58. Functional Diagram of the HMC920LP5E

Additionally, the HMC920LP5E properly sequences gate and drain

voltages to ensure safe on and off operation and offers circuit

self protection in the event of a short circuit. The active bias

controller contains an internal charge pump that generates the

negative voltage needed to drive the VGG1 pin on the

HMC1126ACEZ. Alternatively, an external negative voltage can be

provided.

For more information regarding the use of the HMC920LP5E,

refer to the HMC920LP5E data sheet and the AN-1363

Application Note.

Application Circuit Setup

Figure 59 shows the application circuit for bias control of the

HMC1126ACEZ using the HMC920LP5E. The current through

the HMC920LP5E is measured, and the VGATE output voltage

serves until the setpoint drain current is achieved. The various

external components around the HMC920LP5E are set as follows

in this section.

The target drain current must first be determined and set. This

current must be set based on the maximum drain current

required during operation, including when the device is

generating the maximum expected output power. In this case, a

target drain current of 120 mA was chosen. Set the target value

by attaching a 2.05 kΩ ground referenced resistor to the ISENSE

pin (Pin 25) on the HMC920LP5E.

To ensure adequate headroom, the supply voltage for the

HMC920LP5E must be set higher than the target drain voltage to

the HMC1126ACEZ (5 V). Accordingly, VDD1 and VDD2 on the

HMC920LP5E are set to 5.3 V.

The voltage on the LDOCC pin (Pin 29) on the HMC920LP5E

drives the VDRAIN pins which in turn drive the VDD pin of the

HMC1126ACEZ. Because the LDOCC output is connected to the

VDRAIN output through an internal metal-oxide semiconductor

field effect transistor (MOSFET) switch with an on resistance of

0.5 Ω, the LDOCC voltage (VLDOCC) must be set slightly higher

than the target drain voltage to the HMC1126ACEZ. To

determine the required LDOCC voltage, use the following

equation:

VLDOCC = VDRAIN + IDRAIN × 0.5

Therefore, VLDOCC = 5 V+ (0.12 × 0.5) = 5.06 V.

To set VLDOCC to 5.06 V, use the following equation with R5 set

to 10 kΩ:

R10 = (R5/2) × (VLDOCC − 2)

Therefore, R10 = (10000/2) × (5.06 – 2) = 15.3 kΩ.

Setting VGG1 and VGG2

The VGG2 fixed bias voltage is set to 1 V using a resistor divider that

is derived from VDD1 and VDD2 on the HMC920LP5E. Because

the current into the VGG2 pin is low (<1 mA), large resistor

values in the kΩ range can be used to set the VGG2 voltage and save

on overall current usage.

The recommended minimum voltage for VGG1 into the

HMC1126ACEZ is −2 V, which is also the default value for the

VNEGIN pin on the HMC920LP5E. As a result, there is no need to

adjust the VNEGIN and VGATE voltages.

Refer to the HMC920LP5E data sheet for the detailed schematic.

HMC1126ACEZ-R7 Datasheet(PDF) 17 Page - Analog Devices

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