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AM50DL128CH Datasheet(PDF) 13 Page - Advanced Micro Devices

No. de pieza AM50DL128CH
Descripción Electrónicos  STACKED MULTI-CHIP PACKAGE (MCP) FLASH MEMORY AND SRAM
PDF  64 Pages
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Fabricante Electrónico  AMD [Advanced Micro Devices]
Página de inicio  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM50DL128CH Datasheet(HTML) 13 Page - Advanced Micro Devices

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October 6, 2003
Am50DL128CH
11
ADV ANCE
I N FO RMAT I O N
Table 1.
Device Bus Operations—Flash Word Mode
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, AIN =
Address In, D
IN = Data In, DOUT = Data Out
Notes:
1.
Other operations except for those indicated in this column are
inhibited.
2.
Do not apply CE#f1 or 2 = V
IL, CE1#s = VIL and CE2s = VIH at the
same time.
3.
Active flash is device being addressed.
4.
Don’t care or open LB#s or UB#s.
5.
If WP#/ACC = V
IL , the boot sectors will be protected. If WP#/ACC
= V
IH the boot sectors protection will be removed.
If WP#/ACC = V
ACC (9V), the program time will be reduced by
40%.
6.
The sector protect and sector unprotect functions may also be
implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
7.
If WP#/ACC = V
IL, the two outermost boot sectors remain
protected. If WP#/ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or
unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP#/ACC = V
HH, all sectors will
be unprotected.
8.
Data will be retained in pSRAM.
9.
Data will be lost in pSRAM.
10. CE# inputs on both flash devices may be held low for this operation.
Operation
(Notes 1, 2)
CE#f
Active
CE#f
Inactive CE1#ps CE2ps OE# WE#
Addr.
LB#s
UB#s RESET#
WP#/
ACC
(Note 5)
DQ7–
DQ0
DQ15–
DQ8
(Note 3)
Read from
Active Flash
(Note 8)
LH
HH
LH
A
IN
XX
H
L/H
D
OUT
D
OUT
(Note 9)
H
L
Write to Active
Flash
(Note 8)
LH
HH
HL
A
IN
XX
H
(Note 5)
D
IN
D
IN
(Note 9)
H
L
Standby
V
CC ± 0.3 V
HH
X
X
X
X
X
V
CC ±
0.3 V
H
High-Z
High-Z
Deep Power-down
Standby
V
CC ± 0.3 V
HL
X
X
X
X
X
V
CC ±
0.3 V
H
High-Z
High-Z
Output Disable (Note 10)
L
H
L
H
HH
X
X
X
H
L/H
High-Z
High-Z
HH
X
X
X
Flash Hardware
Reset
(Note 8)
X
HH
X
X
X
X
X
L
L/H
High-Z
High-Z
(Note 9)
H
L
Sector Protect
(Notes 6, 10)
(Note 8)
LH
HH
HL
SADD,
A6 = L,
A1 = H,
A0 = L
XX
V
ID
L/H
D
IN
X
(Note 9)
H
L
Sector
Unprotect
(Notes 6, 10)
(Note 8)
LH
HH
HL
SADD,
A6 = H,
A1 = H,
A0 = L
XX
V
ID
(Note 7)
D
IN
X
(Note 9)
H
L
Temporary
Sector
Unprotect
(Note 8)
X
HH
XX
X
X
X
VID
(Note 7)
DIN
High-Z
(Note 9)
H
L
Read from pSRAM
H
H
L
H
L
H
A
IN
LL
HX
D
OUT
D
OUT
H
L
High-Z
D
OUT
LH
D
OUT
High-Z
Write to pSRAM
H
H
L
H
X
L
A
IN
LL
HX
D
IN
D
IN
H
L
High-Z
D
IN
LH
D
IN
High-Z



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