STPMIC1CPQR datasheet(32/140 Pages) STMICROELECTRONICS

No. de pieza	STPMIC1CPQR

Descripción Electrónicos	Highly integrated power management IC for micro processor units

PDF	140 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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4.3

DDR memory sub-system examples

BUCK2, LDO3 and REFDDR regulators can be used in several possible configurations, to supply various types of

DDR memories.

4.3.1

Powering lpDDR2/lpDDR3 memory

Figure 39. Powering lpDDR2/lpDDR3 memory (LDO3 in bypass mode)

The example in Figure 39. Powering lpDDR2/lpDDR3 memory (LDO3 in bypass mode) shows how to use LDO3

in bypass mode to power supply lpDDR2/3 VDD1 (1.8 V) power domain. LDO3IN is supplied by 1.8 V power

source that is usually from BUCK3 output when BUCK3 is set at 1.8 V to power supply the application processor

VIO power domain. This topology reaches better power efficiency than next example in Figure 40. Powering

lpDDR2/lpDDR3 memory (LDO3 normal mode supplied from VIN).

Figure 40. Powering lpDDR2/lpDDR3 memory (LDO3 normal mode supplied from VIN)

The example in Figure 40. Powering lpDDR2/lpDDR3 memory (LDO3 normal mode supplied from VIN) shows

how to use LDO3 in normal mode to power supply lpDDR2/3 VDD1 (1.8V) power domain. LDO3IN is supplied by

a power source having higher voltage than LDO3OUT (VIN in this example). This topology is suitable for those

applications which do not have 1.8 V power source available from a buck converter.

STPMIC1

DDR memory sub-system examples

DS12792 - Rev 7

page 32/140

STPMIC1CPQR Datasheet(PDF) 32 Page - STMicroelectronics