STPMIC1CPQR datasheet(75/140 Pages) STMICROELECTRONICS

No. de pieza	STPMIC1CPQR

Descripción Electrónicos	Highly integrated power management IC for micro processor units

PDF	140 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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6.3

Control registers

6.3.1

Main control register (MAIN_CR)

Table 25. MAIN_CR

reserved

OCP_OFF_DBG

PWRCTRL_POL

PWRCTRL_EN

RREQ_EN

SWOFF

R/W

Address: 0x10

Type: read/write register

Default: 0x00

Description: main control register. This register is initialized to default values during CHECK&LOAD state.

[7 :5]

Reserved

[4]

OCP_OFF_DBG: Used as software debug bit to emulate OCP turn-OFF event generation. OCP flags coming from any

regulators are bypassed when this bit is set.

0: OCP event is generated based on flags from regulators.

1: OCP turn-OFF event is generated.

[3]

PWRCTRL_POL: specifies PWRCTRL pin polarity

0: PWRCTRL active low

1: PWRCTRL active high

[2]

PWRCTRL_EN: enable PWRCTRL functionality

0: PWRCTRL enable

1: PWRCTRL disable

[1]

RREQ_EN: allows power cycling on turn-OFF condition

0: power cycling is performed only on RSTn assertion by the application processor

1: Power cycling is performed on turn-OFF condition and on RSTn assertion by the application processor

[0]

SWOFF: Software switch OFF bit

0: no effect

1: switch-OFF requested (POWER_DOWN starts immediately)

STPMIC1

Control registers

DS12792 - Rev 7

page 75/140

STPMIC1CPQR Datasheet(PDF) 75 Page - STMicroelectronics

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