STPMIC1CPQR datasheet(57/140 Pages) STMICROELECTRONICS

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Table 13. MAIN/ALTERNATE switch example configuration

Regulator

MAIN setting

ALTERNATE setting

BUCKz(z=1..4)

ENA=1

VOUT=1.2 V,

PREG_MODE=HP

ENA=1

VOUT=0.9 V

PREG_MODE=LP

BUCKx_MAIN_CR=0x61

BUCKx_ALT_CR=0x33

BUCKy(y=1..4)

ENA=1

VOUT=3.3 V

PREG_MODE=HP

ENA=0,

VOUT=3.3 V

PREG_MODE=HP

BUCKy_MAIN_CR=0xD9

BUCKy_ALT_CR=0xD8(or 0x00)

LDOx(x=1,2,5,6)

ENA=1

VOUT=1.8

ENA=0

VOUT=1.8

LDOx_MAIN_CR=0x27

LDOx_ALT_CR=0x26 (or 0x00)

Figure 60. Power mode switch sequence example

MAIN MODE

PWRCTRL

VOUTz (Buck z)

ALTERNATE MODE

POWER_ON

MAIN MODE

1.2 V

0.9 V

VOUTy (Buck y)

3.3 V

0 V

VLDOxOUT (LDO x)

1.8 V

0 V

tSD (BUCK y)

tSU (BUCK y)

tSD (LDO x)

0.2 V

tSS = ΔVOUTy x SR(BUCK Y)

tSS = ΔVLDOxOUT x SR(LDO X)

ΔVOUTz x SR(BUCK Z)

5.4.6

Thermal protection

The STPMIC1 implements a thermal protection to prevent over heating damage.

Junction temperature is permanently monitored thanks to an embed cell.

Protection consists of 2 thresholds :

•

Thermal shutdown threshold (TSHDN), which turns off the STPMIC1

•

Thermal warning threshold (TWRN), which generates an interrupt to be handled by the application processor

Figure 61. Thermal protection thresholds represents the distribution of those thresholds along the temperature

curve.

When the temperature rises above TSHDN_Rise, the STPMIC1 starts a rank down and goes to CHECK&LOAD

state.

If temperature decreases and comes back lower than TSHDN_Fall, the STPMIC1 restarts automatically with

POWER_UP sequence.

In order to allow the application processor to anticipate TSHDN_Rise shutdown and take relevant actions, interrupts

THW_RI and THW_FA are generated when the temperature rises above TWRN_Rise and falls down TWRN_Fall.

Refer to Section 6.5 Interrupt registers about the interruption management.

STPMIC1

Feature description

DS12792 - Rev 7

page 57/140

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