OPA607 datasheet(19/43 Pages) TI

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8.4 Device Functional Modes

The OPAx607 devices have two functional modes: normal operating mode and Power-down ( PD) mode.

8.4.1 Normal Operating Mode

The OPAx607 devices are operational when the power-supply voltage is between 2.2 V (±1.1 V) and 5.5 V

(±2.75 V). Most newer systems use a single power supply to improve efficiency and simplify the power tree

design. The OPAx607 devices can be used with a single-supply power (VS– connected to GND) with no change

in performance from split supply, as long as the input and output pins are biased within the linear operating

region of the device. The valid input and output voltage ranges are given in Section 7.5. The outputs nominally

swing rail-to-rail with approximately 10-mV headroom required for linear operation. The inputs can typically

swing up to the negative rail (typically ground) and to within 1.1 V from the positive supply. Figure 8-6 shows

changing from a ±2.5-V split supply to a 5-V single-supply.

Bias

OPA607

Signal and bias to

next stage

Gain × VSIG

VSIG

5 V

VOUT

Signal and bias from

previous stage

Gain × Bias

OPA607

2.5 V

VOUT

-2.5 V

Signal and bias to

next stage

Gain × VSIG

Gain × Bias

Bias

VSIG

Signal and bias from

previous stage

Figure 8-6. Single-Supply and Dual-Supply Operation

8.4.2 Power-Down Mode

The OPAx607 devices feature a Power-down mode for power critical applications. Under logic control, the

amplifier can be switched from normal operation (consuming ≤ 1 mA) to a Power-down current of less than 1 µA.

When the PD pin is connected high, the amplifier is active. Connecting the PD pin to logic low disables the

amplifier and places the output in a high-impedance state. The output of an op amp is high impedance similar to

a tri-state high-impedance gate under a Power-down condition; however, the feedback network behaves as a

parallel load.

If the Power-down mode is not used, connect PD to the positive supply pin or leave floating. See the Power

Down (Device Enabled When Floating) section in Section 7.5 table for the enable and disable threshold

voltages. The PDpin can be left floating to keep the op amp always enabled, which is primarily possible because

of the presence of an internal pullup resistor within the op amp that, by default, always keeps the PD pin weakly

tied to VS+. However it is also acceptable to strengthen the pull up from the PD pin by connecting a low value

resistance from the PDpin to VS+. This helps make the part less susceptible to noise and transient pick up on the

PD pin. Looking at the PD pin bias current in Figure 7-21 can help us get an accurate understanding of the

voltage required to be applied on the PD pin for enabling and powering down. Note: the hysteresis present in

Figure 7-21 help with single shot power up and power down of OPAx607 devices.

The PDpin exhibits a special type of ESD protection which allows users to apply any voltage between VS– to 6 V

irrespective of the voltage at the VS+. Special ESD structure at the PD pin helps in relaxing the requirements on

power sequencing during power up and power down condition. Refer to Figure 8-4 for details of the internal ESD

structure. The absolute voltage limits applicable on PD pin can be found in Section 7.1 table. Another key care

about in PD condition is to ensure the IN+ and IN– are not exposed to a high differential voltage continuously. In

a power up condition the op-amp's loop gain ensure the IN+ pin and the IN– track each other closely. However in

PD condition the op-amp is inactive and IN– will be usually weakly tied to GND via the RG resistor. Exposing the

IN+ pin continuously to a high voltage in such a condition will result in irreversible offset voltage (VOS) shift.

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OPA607, OPA2607

SBOS981F – OCTOBER 2019 – REVISED SEPTEMBER 2020

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