LPC47M14X datasheet(68/205 Pages) SMSC

68 / 205 page

SMSC DS – LPC47M14X

Page 68

Rev. 03/19/2001

FIFO POLLED MODE OPERATION

With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation.

Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In

this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled

Mode are as follows:

Bit 0=1 as long as there is one byte in the RCVR FIFO.

Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when

in the interrupt mode, the IIR is not affected since EIR bit 2=0.

Bit 5 indicates when the XMIT FIFO is empty.

Bit 6 indicates that both the XMIT FIFO and shift register are empty.

Bit 7 indicates whether there are any errors in the RCVR FIFO.

There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT

FIFOs are still fully capable of holding characters.

Table 31 – Baud Rates

DESIRED

BAUD RATE

DIVISOR USED TO

GENERATE 16X CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL

HIGH

SPEED BIT

2304

0.001

1536

110

1047

134.5

857

0.004

150

768

300

384

600

192

1200

1800

2000

0.005

2400

3600

4800

7200

9600

19200

38400

0.030

57600

0.16

115200

0.16

230400

32770

0.16

460800

32769

0.16

Note

1: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.

Note

2: The High Speed bit is located in the Device Configuration Space.

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