VSC8504-02 datasheet(95/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.6.14

Enhanced LED Control

The following table contains the bits to control advanced functionality of the parallel and serial LED

signals.

10:8

Clock frequency

select

R/W

Select output clock frequency:

000: 25 MHz output clock

001: 125 MHz output clock

010: 31.25 MHz output clock

011–111: Reserved

000

7:6

Reserved

5:4

Clock squelch level

R/W

Select clock squelch level:

00: Automatically squelch clock to low when the

link is not up, is unstable, is up in a mode that

does not support the generation of a recovered

clock (1000BASE-T master or 10BASE-T), or is

up in EEE mode (100BASE-TX or 1000BASE-T

slave).

01: Same as 00 except that the clock is also

generated in 1000BASE-T master and

10BASE-T link-up modes. This mode also

generates a recovered clock output in EEE

mode during reception of LP_IDLE

10: Squelch only when the link is not up

11: Disable clock squelch.

Note: A clock from the SerDes or Cu

PHY will be output on the

recovered clock output in this

mode when the link is down.

Note: A clock from the SerDes or Cu

PHY will be output on the

recovered clock output in this

mode when the link is down.

When the CLK_SQUELCH_IN pin is set high, it

squelches the recovered clocks regardless of

bit settings.

Reserved

2:0

Clock selection for

specified PHY

R/W

000: Serial media recovered clock

001: Copper PHY recovered clock

010–111: Reserved

000

Table 87 •

Enhanced LED Control, Address 25G (0x19)

Bit

Name

Access Description

Default

15:8 LED pulsing duty cycle

control

R/W

Programmable control for LED pulsing

duty cycle when bit 30.12 is set to 1. Valid

settings are between 0 and 198. A setting

of 0 corresponds to a 0.5% duty cycle and

198 corresponds to a 99.5% duty cycle.

Intermediate values change the duty cycle

in 0.5% increments

Table 86 •

Recovered Clock 2 Control, Address 24G (0x18) (continued)

Bit

Name

Access Description

Default

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