ADUM7703 datasheet(4/22 Pages) AD

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ADuM7703

Data Sheet

Rev. 0 | Page 4 of 22

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER REQUIREMENTS

VIN+ > 320 mV

VDD1

4.5

VDD2

5.5

VDD1 Current (IDD1)

8.2

VDD2 Current (IDD2)

Power Dissipation

133

216.5

VDD2 = 4.5 V to 5.5 V

130

211

VDD2 = 3 V to 3.6 V

1 See the Terminology section.

TIMING SPECIFICATIONS

VDD1 = 4.5 V to 20 V, VDD2 = 3 V or 5.5 V, TA = −40°C to +125°C (16-lead SOIC_W), TA = −40°C to +105°C (8-lead SIOC_IC), unless otherwise

noted. Sample tested during initial release to ensure compliance. It is recommended to read MDAT on the MCLKIN rising edge.

Table 2.

Parameter

Limit at TMIN, TMAX

Unit

Description

Min

Typ

Max

fMCLKIN

MHz

Master clock input frequency

tMCLKIN

200

Master clock input period

t11

Data access time after MCLKIN rising edge

t21

Data hold time after MCLKIN rising edge

0.4 × tMCLKIN

Master clock low time

0.4 × tMCLKIN

Master clock high time

1 Defined as the time required from an 80% MCLKIN input level to when the output crosses 0.5 × VDD2 as outlined in Figure 2. Measured with a ±20 μA load and a 25 pF

load capacitance.

Timing Diagram

MCLKIN

MDAT

1SEE NOTE 1 OF TABLE 2 FOR FURTHER DETAILS.

tMCLKIN

80%

0.5 × VDD21

Figure 2. Data Timing Diagram

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