ADF41513 datasheet(4/30 Pages) AD

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ADF41513

Data Sheet

Rev. 0 | Page 4 of 30

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC INPUTS

Input Voltage

High (VIH)

1.4

The serial port interface (SPI) block can accept

both 1.8 V or 3.3 V logic inputs

Low (VIL)

0.6

Input Current (IINH, IINL)

±1

µA

Input Capacitance (CIN)

LOGIC OUTPUTS

Output Voltage

High (VOH)

1.4

MUXOUT voltage = 1.8 V, DLD voltage = 1.8 V

2.6

MUXOUT voltage = 3.3 V, DLD voltage = 3.3 V

Low (VOL)

0.4

Output High Current, Output Low

Current (IOH, IOL)

500

µA

POWER SUPPLIES

AVDD1, AVDD2, AVDD3, AVDD4, AVDD5, VP

3.135

3.3

3.465

IDD11

3.2

Current drawn by AVDD1

IDD21

63.5

Current drawn by AVDD2

IDD31

2.1

3.6

Current drawn by AVDD3

IDD41

1.45

Current drawn by AVDD4

IDD51

Current drawn by AVDD5

Current drawn by VP

ITOTAL

95.1

128.8

Total current drawn by AVDDx and VP

Power-Down Mode

100

µA

TA = 25°C, CE is low, total of all rails

NOISE CHARACTERISTICS

Normalized Phase Noise Floor

(PNSYNTH)

In Integer N Mode2

−235

dBc/Hz

PLL loop bandwidth (BW) = 1 MHz (Integer N

mode)

In Fractional-N Mode3

−231

dBc/Hz

PLL loop BW = 1 MHz (fractional-N mode)

Normalized 1∕f Noise (PN1_f)3

−128

dBc/Hz

10 kHz offset, normalized to 1 GHz

SPURIOUS SIGNALS

Reference Spurious

−90

dBc

At reference = 100 MHz, PLL loop BW = 40 kHz

PFD Spurious

−87

dBc

At PFD = 50 MHz, PLL loop BW = 40 kHz

In-Band Integer Boundary

Spurious

−45

dBc

10 kHz offset, PLL loop BW = 250 kHz

TA = 25°C, AVDDx = 3.3 V (where x = 1, 2, 3, or 4), prescaler (P) = 8/9, fRFIN = 26.5 GHz, REFIN = 124 MHz, PFD frequency input (fPFD) = 124 MHz.

The synthesizer phase noise floor is estimated by measuring the inband phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value)

and 10 log fPFD. PNSYNTH is the total phase noise measured at the VCO output (PNTOT) − 10 log fPFD − 20 log N.

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,

and at a frequency offset, f, is given by phase noise (PN) = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are

modeled in the ADIsimPLL.

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