GD25LQ64CSFS datasheet(34/77 Pages) GIGADEVICE

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1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LQ64C

Figure18. 32KB Block Erase Sequence Diagram

Command

52H

CS#

SCLK

29 30 31

MSB

24 Bits Address

23 22

Figure18a. 32KB Block Erase Sequence Diagram (QPI)

CS#

SCLK

IO0

IO1

IO2

IO3

Command

52H

A23-16 A12-8

A7-0

7.18 64KB Block Erase (BE) (D8H)

The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command

must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is

entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is

a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.

The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-byte

address on SI  CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth

bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon

as CS# is driven high, the self-timed Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase cycle is in

progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress

(WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the

cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which

is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.

GD25LQ64CSFS Datasheet(PDF) 34 Page - GigaDevice Semiconductor (Beijing) Inc.