GD25LQ64CSFS datasheet(23/77 Pages) GIGADEVICE

23 / 77 page

1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LQ64C

Fast Read (0BH) in QPI mode

The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is configured by

the

“Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either

maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting,

the number of dummy clocks can be configured as either 4/6/8.

Figure8a. Read Data Bytes at Higher Speed Sequence Diagram (QPI)

CS#

SCLK

IO0

IO1

IO2

IO3

Command

0BH

A23-16 A15-8

A7-0

Dummy*

12 13

IOs switch from

Input to output

Byte1

*"Set Read Parameters" Command (C0H)

can set the number of dummy clocks

Dummy*

7.8 Dual Output Fast Read (3BH)

The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being

latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.

The command sequence is shown in followed Figure9. The first byte addressed can be at any location. The address is

automatically incremented to the next higher address after each byte of data is shifted out.

Figure9. Dual Output Fast Read Sequence Diagram

Command

3BH

CS#

SCLK

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

MSB

34 35 36 37

38 39

Data Out1

42 43 44 45

46 47

Data Out2

CS#

SCLK

MSB

Dummy Clocks

GD25LQ64CSFS Datasheet(PDF) 23 Page - GigaDevice Semiconductor (Beijing) Inc.

GD25LQ64CSFS Datasheet(HTML) 23 Page - GigaDevice Semiconductor (Beijing) Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Descarga

Enlace URL