GD25LQ64CSJS datasheet(35/77 Pages) GIGADEVICE

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1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LQ64C

Figure19. 64KB Block Erase Sequence Diagram

Command

D8H

CS#

SCLK

29 30 31

MSB

24 Bits Address

23 22

Figure19a. 64KB Block Erase Sequence Diagram (QPI)

CS#

SCLK

IO0

IO1

IO2

IO3

Command

D8H

A23-16 A15-8

A7-0

22 18

21 17

7.19 Chip Erase (CE) (60/C7H)

The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously

have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS#

Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the

sequence.

The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. The

command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the command code has been

latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase

cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to

check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase

cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)

bit is reset. The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or

the Block Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. The Chip Erase (CE) command is ignored if one or more

sectors are protected.

GD25LQ64CSJS Datasheet(PDF) 35 Page - GigaDevice Semiconductor (Beijing) Inc.