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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Detailed Description

6.10 DMA Controllers

6.10.1 PDMA Controller

The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer

needs of peripherals, which perform data transfers using memory mapped registers accessed via a

standard non-coherent bus fabric. The PDMA module is intended to be located close to one or more

peripherals which require an external DMA for data movement and is architected to reduce cost by using

VBUSP interfaces and supporting only statically configured Transfer Request (TR) operations.

The PDMA is only responsible for performing the data movement transactions which interact with the

peripherals themselves. Data which is read from a given peripheral is packed by a PDMA source channel

into a PSI-L data stream which is then sent to a remote peer UDMA-P destination channel which then

performs the movement of the data into memory. Likewise, a remote UDMA-P source channel fetches

data from memory and transfers it to a peer PDMA destination channel over PSI-L which then performs

the writes to the peripheral.

The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer

complexity at each point in the system to match the requirements of whatever is being transferred to or

from. Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their

FIFO dimensioning requirements, so the PDMA transfer engines are kept simple with only a few

dimensions (typically for sample size and FIFO depth), hardcoded address maps, and simple triggering

capabilities.

Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous

transfer operations to be ongoing. The DMA controller maintains state information for each of the channels

and employs round-robin scheduling between channels in order to share the underlying DMA hardware.

There are five PDMA modules in the device.

6.10.1.1 PDMA Features

6.10.1.1.1 MCU_PDMA0 Features

The MCU domain PDMA0 supports the following features:

•

Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)

•

Provides 0 memory write access units

•

Provides 1 memory read access unit (Read Unit 0):

–

Supports 1 outstanding read per interface (VBUSP)

–

Supports read burst up to 32 bytes (limited by Rx Per-Channel FIFO depth)

–

Provides a 32-bit wide VBUSP read only master interface for peripheral accesses

•

Supports up to 0 simultaneous destination (Tx) channels

•

Supports up to 4 simultaneous source (Rx) channels

•

Supports static Transfer Requests (TRs) only

•

Supports MCAN special transfer mode

•

Provides per-channel buffering:

–

Provides 8x128-bit word deep data FIFO for each destination channel

–

Provides 8x128-bit word deep data FIFO for each source channel

–

Provides 128-bit wide PSI-L compliant data interface to remote UDMA and remote peripherals

–

Includes 1 output event transport lane

–

Provides 128-bit wide PSI-L compliant data interface from remote UDMA and remote peripherals

–

Includes 1 input event transport lane

6.10.1.1.2 MCU_PDMA1 Features

The MCU domain PDMA1 supports the following features:

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