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AM652X Datasheet(PDF) 94 Page - Texas Instruments

No. de pieza AM652X
Descripción Electrónicos  Sitara Processors
PDF  299 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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AM652X Datasheet(HTML) 94 Page - Texas Instruments

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AM6548, AM6528, AM6546
AM6526, AM6527
SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527
Terminal Configuration and Functions
Copyright © 2017–2018, Texas Instruments Incorporated
Table 4-54. PRU-ICSSG2 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
PRG2_PWM3_A2
PRU_ICSSG PWM Output A
IO
AH15
PRG2_PWM3_B0
PRU_ICSSG PWM Output B
IO
AG18
PRG2_PWM3_B1
PRU_ICSSG PWM Output B
IO
AE17
PRG2_PWM3_B2
PRU_ICSSG PWM Output B
IO
AC16
PRG2_RGMII1_RXC
PRU_ICSSG RGMII Receive Clock
I
AF17
PRG2_RGMII1_RX_CTL
PRU_ICSSG RGMII Receive Control
I
AG17
PRG2_RGMII1_TXC
PRU_ICSSG RGMII Transmit Clock
IO
AD16
PRG2_RGMII1_TX_CTL
PRU_ICSSG RGMII Transmit Control
O
AE17
PRG2_RGMII2_RXC
PRU_ICSSG RGMII Receive Clock
I
AG15
PRG2_RGMII2_RX_CTL
PRU_ICSSG RGMII Receive Control
I
AG14
PRG2_RGMII2_TXC
PRU_ICSSG RGMII Transmit Clock
IO
AE14
PRG2_RGMII2_TX_CTL
PRU_ICSSG RGMII Transmit Control
O
AC17
PRG2_RGMII1_RD0
PRU_ICSSG RGMII Receive Data
I
AF18
PRG2_RGMII1_RD1
PRU_ICSSG RGMII Receive Data
I
AE18
PRG2_RGMII1_RD2
PRU_ICSSG RGMII Receive Data
I
AH17
PRG2_RGMII1_RD3
PRU_ICSSG RGMII Receive Data
I
AG18
PRG2_RGMII1_TD0
PRU_ICSSG RGMII Transmit Data
O
AH16
PRG2_RGMII1_TD1
PRU_ICSSG RGMII Transmit Data
O
AG16
PRG2_RGMII1_TD2
PRU_ICSSG RGMII Transmit Data
O
AF16
PRG2_RGMII1_TD3
PRU_ICSSG RGMII Transmit Data
O
AE16
PRG2_RGMII2_RD0
PRU_ICSSG RGMII Receive Data
I
AH15
PRG2_RGMII2_RD1
PRU_ICSSG RGMII Receive Data
I
AC16
PRG2_RGMII2_RD2
PRU_ICSSG RGMII Receive Data
I
AD17
PRG2_RGMII2_RD3
PRU_ICSSG RGMII Receive Data
I
AH14
PRG2_RGMII2_TD0
PRU_ICSSG RGMII Transmit Data
O
AD15
PRG2_RGMII2_TD1
PRU_ICSSG RGMII Transmit Data
O
AF14
PRG2_RGMII2_TD2
PRU_ICSSG RGMII Transmit Data
O
AC15
PRG2_RGMII2_TD3
PRU_ICSSG RGMII Transmit Data
O
AD14
PRG2_UART0_CTSn
PRU-ICSSG UART Clear to Send (active low)
I
AD12
PRG2_UART0_RTSn
PRU-ICSSG UART Request to Send (active low)
O
AH12
PRG2_UART0_RXD
PRU-ICSSG UART Receive Data
I
AE12
PRG2_UART0_TXD
PRU-ICSSG UART Transmit Data
O
AF12
4.3.22 SERDES
4.3.22.1 MAIN Domain
Table 4-55. SERDES0 Signal Descriptions(1)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
SERDES0_REFCLKN
SERDES Clock Input (negative)
I
AG5
SERDES0_REFCLKP
SERDES Clock Input (positive)
I
AG6
SERDES0_REFRES
SERDES Reference Resistor(2)
A
AC9
SERDES0_RXN
SERDES Differential Receive Data (negative)
I
AH3
SERDES0_RXP
SERDES Differential Receive Data (positive)
I
AG2
SERDES0_TXN
SERDES Differential Transmit Data (negative)
O
AH4
SERDES0_TXP
SERDES Differential Transmit Data (positive)
O
AG3



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