HIP2103, HIP2104

FN8276 Rev 0.00

Page 9 of 21

November 27, 2013

Time Delay to Set Sleep Mode

(Note 14, Figure 4)

HI = LI = 0 -> 1

17

927

µs

Time Delay to Reset Sleep Mode

(Note 14, Figure 4)

HI = 0, LI = 0 -> 1

17

927

µs

NOTE:

14. When HI and LI are on simultaneously, HO and LO are never on simultaneously. This feature is intended to initiate sleep. This feature cannot be used

to prevent shoot-through for normal alternating switching between LI and HI. Dead time must be provided when HI = 0 -> LI = 1, or LI = 0 -> HI = 1.

See Timing Diagrams (Figure 4).

load = 1µF (HIP2104 only) Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued)

PARAMETERS

SYMBOL

TEST CONDITIONS

UNITS

MIN

TYP

MAX

MIN

MAX

Timing Diagrams

FIGURE 3. VDD POWER-ON/OFF TIMING FOR SLEEP MODE

2M

 to HS

2M

 to HS

100

 to LS

100

 to LS

HO = Logic inputs

LO = Logic inputs

UV threshold

HO

LO

*SLEEP

UVLO

VDD

VDen

VCC

VCen

HO

LO

*SLEEP

UVLO

VDD

VDen

VCC

VCen

(Vden and VCen apply to HIP2104 only)

*Sleep is an internal state. Minimal IDD or IBAT current results when active (high).