HIP2103, HIP2104

FN8276 Rev 0.00

Page 3 of 21

November 27, 2013

Pin Configurations

HIP2103

(8 LD 3x3 TDFN)

TOP VIEW

HIP2104

(12 LD 4x4 DFN)

TOP VIEW

EPAD

(VSS)

1

2

3

4

8

7

6

5

VDD

HI

LI

VSS

HB

HO

HS

LO

EPAD

(VSS)

1

2

3

4

12

11

10

9

8

VDen

VCen

VCC

VDD

HI

VBAT

HB

HO

HS

LO

6

5

LI

7

VSS

Pin Descriptions

HIP2103

HIP2104

SYMBOL

DESCRIPTION

8 LD

TDFN

12 LD

DFN

-

1

VDen

1ms debouncing period.

-

2

VCen

1ms debouncing period.

-

3

VCC

(HIP2104 only) 3.3V output voltage of linear regulator, 75mA. Enabled by VCen.

1

4

VDD

(HIP2103) Input voltage 14V max.

(HIP2104) 0utput voltage of linear regulator, 12V nominal, 75mA. Enabled by VDen.

25

HI

High side input, 3.3V or 5V logic compatible. (HI -> HO).

36

LI

Low side Input, 3.3V or 5V logic compatible. (LI -> LO).

47

VSS

Signal ground.

58

LO

Low side driver Output. (LI ->LO).

69

HS

High side FET Source connection (low side boot capacitor connection).

710

HO

High side driver Output. (HI -> HO)

811

HB

High side Boot capacitor.

-

12

VBAT

(HIP2104 only) Positive battery (bridge voltage) connection.

EP

EP

EPAD

Exposed Pad, must be connected to signal ground.