AD9975ABSTEB datasheet(19/20 Pages) AD

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AD9975

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Bit 1: ADC Output on Falling RXCLK

If Bit 1 is set high, the TX path data will be sampled on the falling

edge of RXCLK. When this bit is low, the data will be sampled on

the rising edge of RXCLK.

Bit 3: Three-State RX Port

This bit sets the receive output RX[5:0] into a high impedance

three-state mode. It allows for sharing the bus with other devices.

Bit 4: CLK-A Output Disable

Setting Bit 4 high fixes the CLK-A output to a Logic 0 output level.

Bit 5: CLK-B Output Disable

Setting Bit 5 high fixes the CLK-A output to a Logic 0 output level.

Bit 6: CLK-A Equal to OSC IN

Setting Bit 6 high sets the CLK-A output signal frequency equal

to the OSC IN signal frequency. Otherwise, the CLK-A output

frequency is equal to FOSCIN

× L.

Bit 7: CLK-B Equal to OSC IN/4

Setting Bit 7 high sets the CLKB output signal frequency equal

to the OSC IN/4 signal frequency. Otherwise, the CLKB output

frequency is equal to OSC IN/2.

This register stores the die revision of the chip. It is a read-only

PCB DESIGN CONSIDERATIONS

Although the AD9975 is a mixed signal device, the part should

be treated as an analog component. The digital circuitry on-chip

has been specially designed to minimize the impact that the

digital switching noise will have on the operation of the analog

circuits. Following the power, grounding, and layout recom-

mendations in this section will help you get the best performance

from the MxFE.

Component Placement

If the three following guidelines of component placement are

followed, chances for getting the best performance from the

MxFE are greatly increased. First, manage the path of return cur-

rents flowing in the ground plane so that high frequency switching

currents from the digital circuits do not flow on the ground plane

under the MxFE or analog circuits. Second, keep noisy digital

signal paths and sensitive receive signal paths as short as possible.

Third, keep digital (noise generating) and analog (noise suscep-

tible) circuits as far away from each other as possible.

In order to best manage the return currents, pure digital circuits

that generate high switching currents should be closest to the

power supply entry. This will keep the highest frequency return

current paths short and prevent them from traveling over the

sensitive MxFE and analog portions of the ground plane. Also,

these circuits should be generously bypassed at each device that

will further reduce the high frequency ground currents. The

MxFE should be placed adjacent to the digital circuits such that

the ground return currents from the digital sections will not flow

in the ground plane under the MxFE. The analog circuits should

be placed furthest from the power supply.

The AD9975 has several pins that are used to decouple sensitive

internal nodes. These pins are REFIO, REFB, and REFT. The decou-

pling capacitors connected to these points should have low ESR

and ESL. These capacitors should be placed as close to the MxFE

as possible and be connected directly to the analog ground plane.

The resistor connected to the FS ADJ pin should also be placed

close to the device and connected directly to the analog ground plane.

Power Planes and Decoupling

The AD9975 evaluation board demonstrates a good power supply

distribution and decoupling strategy. The board has four layers;

two signal layers, one ground plane, and one power plane. The

power plane is split into a 3VDD section, which is used for the

3V digital logic circuits; a DVDD section, which is used to supply

the digital supply pins of the AD9975; an AVDD section, which

is used to supply the analog supply pins of the AD9975; and a

VANLG section, which supplies the higher voltage analog com-

ponents on the board. The 3VDD section will typically have the

highest frequency currents on the power plane and should be

kept the furthest from the MxFE and analog sections of the board.

The DVDD portion of the plane brings the current used to power

the digital portion of the MxFE to the device. This should be

treated similar to the 3VDD power plane and be kept from

going underneath the MxFE or analog components. The MxFE

should largely sit on the AVDD portion of the power plane.

The AVDD and DVDD power planes may be fed from the same

low noise voltage source; however, they should be decoupled

from each other to prevent the noise generated in the DVDD

portion of the MxFE from corrupting the AVDD supply. This

can be done by using ferrite beads between the voltage source and

DVDD and between the source and AVDD. Both DVDD and

AVDD should have a low ESR, bulk decoupling capacitor on the

MxFE side of the ferrite as well as a low ESR, ESL decoupling

capacitors on each supply pin (i.e., the AD9975 requires five

power supply decoupling caps, one each on Pins 5, 38, 47, 14, and

35). The decoupling caps should be placed as close to the MxFE

supply pins as possible. An example of the proper decoupling is

shown in the AD9975 evaluation board schematic.

Ground Planes

In general, if the component placing guidelines discussed earlier

can be implemented, it is best to have at least one continuous

ground plane for the entire board. All ground connections should

be made as short as possible. This will result in the lowest imped-

ance return paths and the quietest ground connections.

If the components cannot be placed in a manner that would keep

the high frequency ground currents from traversing under the

MxFE and analog components, it may be necessary to put current

steering channels into the ground plane to route the high frequency

currents around these sensitive areas. These current steering

channels should be made only when and where necessary.

Signal Routing

The digital RX and TX signal paths should be kept as short as

possible. Also, the impedance of these traces should have a con-

trolled impedance of about 50

Ω. This will prevent poor signal

integrity and the high currents that can occur during undershoot

or overshoot caused by ringing. If the signal traces cannot be kept

shorter than about 1.5 inches, then series termination resistors

(33

Ω to 47 Ω) should be placed close to all signal sources. It is

a good idea to series terminate all clock signals at their source

regardless of trace length.

The receive RX+/RX– signals are the most sensitive signals on the

entire board. Careful routing of these signals is essential for good

receive path performance. The RX+/RX– signals form a differential

pair and should be routed together as a pair. By keeping the traces

adjacent to each other, noise coupled onto the signals will appear

as common mode and will be largely rejected by the MxFE receive

input. Keeping the driving point impedance of the receive signal low

and placing any low-pass filtering of the signals close to the MxFE

will further reduce the possibility of noise corrupting these signals.

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