AD9975ABSTEB datasheet(16/20 Pages) AD

16 / 20 page

REV. 0

–16–

AD9975

INSTRUCTION BIT n

INSTRUCTION BIT n–1

SCLK

SDATA

tDV

Figure 6. Timing Diagram Register Read from AD9975

MSB/LSB Transfers

The AD9975 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. The

bit order is controlled by the SPI LSB First Bit (Register 0, Bit 6).

The default value is 0, MSB first. Multibyte data transfers in

MSB format can be completed by writing an instruction byte

that includes the register address of the last address to be accessed.

The AD9975 will automatically decrement the address for each

successive byte required for the multibyte communication cycle.

When the SPI LSB First Bit (Register 0, Bit 6) is set high, the

serial port interprets both instruction and data bytes LSB first.

Multibyte data transfers in LSB format can be completed by

writing an instruction byte that includes the register address of

the first address to be accessed. The AD9975 will automatically

increment the address for each successive byte required for the

multibyte communication cycle.

Figures 7a and 7b show how the serial port words are built for

each of these modes.

SCLK

SDATA

SENABLE

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

R/W

I6(n) I5(n) I4

D7n D6n

D6n D7n

Figure 7a. Serial Register Interface Timing MSB First

SCLK

SDATA

SENABLE

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

I5(n) I6(n)

D00 D10 D20

D6n D7n

R/W

Figure 7b. Serial Register Interface Timing LSB First

Notes on Serial Port Operation

The serial port is disabled and all registers are set to their default

values during a hardware reset. During a software reset, all regis-

ters except Register 0 are set to their default values. Register 0

will remain at the last value sent, with the exception that the

Software Reset Bit will be set to 0.

Table V. Register Layout

Address

Default

(hex)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(hex)

Type

Select 4-Wire LSB/MSB

Software

R/W

SPORT

First

Reset

Power-

Power-Down Power-Down Power-

Power-Down 00

R/W

Down

Interpolators RX Reference Down ADC Receive Filter

PLL-A

DAC

and SPGA

and CPGA

R/W

ADC Clock

PLL-A (xL)

R/W

Source

Multiplier [1:0]

OSC IN/2

RX LPF

RX Path

RX Digital Fast ADC

Wideband RX Enable

RX LPF

R/W

Tuning

DC Offset HPF

Sampling

LPF

1-Pole

Bypass

Update

Update in

Correction Bypass

RX LPF

Disable

Progress

RX LPF Filter Tuning Target [7:0]

R/W

RXBOOST

RXBOOST PGA Gain

RX PGA Gain [4:0]

R/W

Active Low

Setting

through

TX Interpolation Filter Select

Sample TX TX Data

R/W

on Falling

Input Twos

TXCLKIN Complement

CLK-B Equal CLK-A

CLK-B

CLK-A

Three-State

ADC Output RX Data

R/W

to OSC IN/4

Equal

Output

RX Port

on Falling

Output Twos

to OSC IN Disable

Disable

RXCLK

Complement

Version [3:0]

AD9975ABSTEB Datasheet(PDF) 16 Page - Analog Devices

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