X5083

Characteristics subject to change without notice.

6 of 21

REV 1.1.6 6/25/02

www.xicor.com

Write Enable Latch

The device contains a Write Enable Latch. This latch

must be SET before a Write Operation is initiated. The

WREN instruction will set the latch and the WRDI

instruction will reset the latch (Figure 7). This latch is

automatically reset upon a power-up condition and

after the completion of a valid Write Cycle.

Status Register

The RDSR instruction provides access to the status

register. The status register may be read at any time,

even during a write cycle. The status register is format-

ted as follows.

Status Register/Block Lock/WDT Byte

Block Lock Memory

Xicor’s block lock memory provides a flexible mecha-

nism to store and lock system ID and parametric infor-

mation. There are seven distinct block lock memory

areas within the array which vary in size from one page

to as much as half of the entire array. These areas and

associated address ranges are block locked by writing

the appropriate two byte block lock instruction to the

device as described in Table 1 and Figure 9. Once a

block lock instruction has been completed, that block

lock setup is held in the nonvolatile status register until

the next block lock instruction is issued. The sections

of the memory array that are block locked can be read

but not written until block lock is removed or changed.

765

4

3

21

0

0

0

0

WD1

WD0

BL2

BL1

BL0

Table 1. Instruction Set and Block Lock Protection Byte Definition

Instruction Format

Instruction Name and Operation

0000 0110

WREN: set the write enable latch (write enable operation)

0000 0100

WRDI: reset the write enable latch (write disable operation)

0000 0001

Write status instruction—followed by:

Block lock/WDT byte: (See Figure 1)

--->none of the array

0000 0101

READ STATUS: reads status register & provides write in progress status on SO pin

0000 0010

WRITE: write operation followed by address and data

0000 0011

READ: read operation followed by address

Watchdog Timer

The watchdog timer bits, WD0 and WD1, select the

watchdog time out period. These nonvolatile bits are

programmed with the WRSR instruction. A change to

the Watchdog Timer, either setting a new time out

period or turning it off or on, takes effect, following

either the next command (read or write) or cycling the

power to the device.

The recommended procedure for changing the Watch-

dog Timer settings is to do a WREN, followed by a

write status register command. Then execute a soft-

ware loop to read the status register until the MSB of

the status byte is zero. A valid alternative is to do a

WREN, followed by a write status register command.

Then wait 10ms and do a read status command.

Table 2. Watchdog Timer Definition

Status Register Bits

Watchdog Time Out

(Typical)

WD1

WD0

0

0

1.4 seconds

0

1

600 milliseconds

1

0

200 milliseconds

1

1

disabled (factory default)