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STM32L471RG Datasheet(PDF) 197 Page - STMicroelectronics |
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STM32L471RG Datasheet(HTML) 197 Page - STMicroelectronics |
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197 / 218 page  DocID027226 Rev 1 197/218 STM32L471xx Electrical characteristics 199 NAND controller waveforms and timings Figure 44 through Figure 47 represent synchronous waveforms, and Table 100 and Table 101 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x02 • COM.FMC_WaitSetupTime = 0x03 • COM.FMC_HoldSetupTime = 0x02 • COM.FMC_HiZSetupTime = 0x03 • ATT.FMC_SetupTime = 0x01 • ATT.FMC_WaitSetupTime = 0x03 • ATT.FMC_HoldSetupTime = 0x02 • ATT.FMC_HiZSetupTime = 0x03 • Bank = FMC_Bank_NAND • MemoryDataWidth = FMC_MemoryDataWidth_16b • ECC = FMC_ECC_Enable • ECCPageSize = FMC_ECCPageSize_512Bytes • TCLRSetupTime = 0 • TARSetupTime = 0 In all timing tables, the THCLK is the HCLK clock period. Table 99. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FMC_CLK period 2THCLK-0.5 - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2 td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK+0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2.5 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 5 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK-1 - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2 td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK-1 - td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 4.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 1.5 - td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK+1 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 0 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 - 1. CL = 30 pF. 2. Guaranteed by characterization results. |
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