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STM32F101XF Datasheet(PDF) 13 Page - STMicroelectronics

No. de pieza STM32F101XF
Descripción Electrónicos  Single-cycle multiplication and hardware division
PDF  117 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F101XF Datasheet(HTML) 13 Page - STMicroelectronics

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STM32F101xF, STM32F101xG
Description
Figure 2. Clock tree
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.



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