STM32F078CB datasheet(61/120 Pages) STMICROELECTRONICS

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STM32F078CB, STM32F078RB, STM32F078VB

Electrical characteristics

6.3.5

Wakeup time from low-power mode

The wakeup times given in Table 33 are the latency between the event and the execution of

the first user instruction. The device goes in low-power mode after the WFE (Wait For

Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles

must be added to the following timings due to the interrupt latency in the Cortex M0

architecture.

The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.

During wakeup from Stop mode, SYSCLK takes the default setting: HSI 8 MHz.

The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.

All timings are derived from tests performed under the ambient temperature and supply

voltage conditions summarized in Table 23: General operating conditions.

6.3.6

External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,

the recommended clock input waveform is shown in Figure 14: High-speed external clock

source AC timing diagram

Table 33. Low-power mode wakeup timings

Symbol

Parameter

Typ @ VDDA

Max

Unit

= 1.8 V

= 3.3 V

tWUSTOP

Wakeup from Stop mode

3.5

2.8

5.3

µs

tWUSLEEP

Wakeup from Sleep mode

4 SYSCLK cycles

µs

Table 34. High-speed external user clock characteristics

Symbol

Parameter(1)

1. Guaranteed by design, not tested in production.

Min

Typ

Max

Unit

fHSE_ext User external clock source frequency

MHz

VHSEH

OSC_IN input pin high level voltage

0.7 VDDIOx

-VDDIOx

VHSEL

OSC_IN input pin low level voltage

VSS

0.3 VDDIOx

tw(HSEH)

tw(HSEL)

OSC_IN high or low time

tr(HSE)

tf(HSE)

OSC_IN rise or fall time

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