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STM8SPLNB1 Datasheet(PDF) 23 Page - STMicroelectronics |
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STM8SPLNB1 Datasheet(HTML) 23 Page - STMicroelectronics |
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23 / 44 page ![]() DocID018831 Rev 5 23/44 STM8SPLNB1 Electrical characteristics 43 4.3 Operating conditions 4.3.1 General operating conditions Table 22. General operating conditions Symbol Parameter Conditions Min Max Unit fCPU Internal CPU clock frequency - 0 16 MHz VDD Standard operating voltage - 2.95 5.5 V VCAP(1) 1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range. CEXT: capacitance of external capacitor - 470 3300 nF ESR of external capacitor at 1 MHz(2) 2. This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator. - 0.3 ESL of external capacitor - 15 nH PD(3) 3. To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/ JA (see 5.3: Thermal characteristics) Power dissipation at TA = 85 °C TSSOP20 - 238 mW SO20W - 220 UFQFPN20 - 220 TA Ambient temperature Maximum power dissipation -40 85 °C TJ Junction temperature range - -40 105 Table 23. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Typ Max Unit tVDD VDD rise time rate - 2 - - μs/V VDD fall time rate(1) 1. Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the minimum operating voltage (VDD min.) when the tTEMP delay has elapsed. -2 - - tTEMP Reset release delay VDD rising - - 1.7 ms VIT+ Power-on reset threshold - 2.6 2.7 2.85 V VIT- Brown-out reset threshold - 2.5 2.65 2.8 VHYS(BOR) Brown-out reset hysteresis - - 70 - mV |
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