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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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ST72361AR4-Auto Datasheet(PDF) 212 Page - STMicroelectronics |
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ST72361AR4-Auto Datasheet(HTML) 212 Page - STMicroelectronics |
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212 / 279 page  LINSCI serial communication interface (LIN master only) ST72361xx-Auto 212/279 Doc ID 12468 Rev 3 Note: This RR factor is used only when the ERPR fine tuning factor is equal to 00h; otherwise, RR is replaced by the (RR*ERPR) dividing factor. 16.8.7 Extended receive prescaler division register (SCIERPR) Read/ write Reset value: 0000 0000 (00h) Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register. The extended baud rate generator is activated when a value other than 00h is stored in this register. The clock frequency from the 16 divider (see Figure 90) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255). The extended baud rate generator is not active after a reset. 16.8.8 Extended transmit prescaler division register (SCIETPR) Read/ write Reset value: 0000 0000 (00h) Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register. The extended baud rate generator is activated when a value other than 00h is stored in this register. The clock frequency from the 16 divider (see Figure 90) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255). The extended baud rate generator is not active after a reset. Table 79. Receiver rate divider RR dividing factor SCR2 SCR1 SCR0 1 0 0 0 21 4 1 0 81 16 1 0 0 32 1 64 1 0 128 1 7 0 ERPR7 ERPR6 ERPR5 ERPR4 ERPR3 ERPR2 ERPR1 ERPR0 7 0 ETPR7 ETPR6 ETPR5 ETPR4 ETPR3 ETPR2 ETPR1 ETPR0 |
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