ST72361AR4-Auto datasheet(68/279 Pages) STMICROELECTRONICS

68 / 279 page

Power saving modes

ST72361xx-Auto

68/279

Doc ID 12468 Rev 3

Figure 30.

AWUF halt timing diagram

Figure 31.

AWUFH mode flow-chart

Note:

WDGHALT is an option bit. See option byte section for more details.

Peripheral clocked with an external clock source can still be active.

Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode

(such as external interrupt). Refer to Table 16 for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the

CC register are set to the current software priority level of the interrupt routine and

recovered when the CC register is popped.

AWUFH interrupt

fCPU

RUN MODE

HALT MODE

256 or 4096 tCPU

RUN MODE

fAWU_RC

Clear

by software

tAWU

RESET

INTERRUPT 3)

CPU

MAIN OSC

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

MAIN OSC

PERIPHERALS

I[1:0] BITS

OFF

XX 4)

CPU

MAIN OSC

PERIPHERALS

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT 1)

WATCHDOG

RESET

CYCLE

AWU RC OSC

OFF

AWU RC OSC

OFF

HALT INSTRUCTION

(MCCSR.OIE=0)

(AWUCSR.AWUEN=1)

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