ST72361AR4-Auto datasheet(204/279 Pages) STMICROELECTRONICS

No. de pieza	ST72361AR4-Auto

Descripción Electrónicos	Clock, reset and supply management

PDF	279 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

Logo

204 / 279 page

LINSCI serial communication interface (LIN master only)

ST72361xx-Auto

204/279

Doc ID 12468 Rev 3

Note:

The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled

(TE and RE = 0), the SCLK and TDO pins go into high impedance state.

The LBCL, CPOL and CPHA bits have to be selected before enabling the transmitter to

ensure that the clock pulses function correctly. These bits should not be changed while the

transmitter is enabled.

Figure 91.

SCI example of synchronous and asynchronous transmission

Figure 92.

SCI data clock timing diagram (M = 0)

Asynchronous

Synchronous

(e.g. modem)

(e.g. shift register)

RDI

TDO

SCLK

Output port

Enable

Clock

Data in

Data out

SCI

M = 0 (8 data bits)

Clock (CPOL=0, CPHA=1)

Clock (CPOL=1, CPHA=0)

Clock (CPOL=1, CPHA=1)

Start

LSB

MSB Stop

* LBCL bit controls last data clock pulse

Start

Idle or preceding

transmission

Data

Stop

Clock (CPOL=0, CPHA=0)

Idle or next

transmission

ST72361AR4-Auto Datasheet(PDF) 204 Page - STMicroelectronics

ST72361AR4-Auto Datasheet(HTML) 204 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL