ST7FOXU0 datasheet(42/123 Pages) STMICROELECTRONICS

42 / 123 page

Interrupts

ST7FOXU0

42/123

Interrupts

The ST7 core may be interrupted by one of two different methods: Maskable hardware

interrupts as listed in the “interrupt mapping” table and a non-maskable software interrupt

(TRAP). The Interrupt processing flowchart is shown in Figure 16.

The maskable interrupts must be enabled by clearing the I bit in order to be serviced.

However, disabled interrupts may be latched and processed when they are enabled (see

external interrupts subsection).

Note:

After reset, all interrupts are disabled.

When an interrupt has to be serviced:

●

Normal processing is suspended at the end of the current instruction execution.

●

The PC, X, A and CC registers are saved onto the stack.

●

The I bit of the CC register is set to prevent additional interrupts.

●

The PC is then loaded with the interrupt vector of the interrupt to service and the first

instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table

for vector addresses).

The interrupt service routine should finish with the IRET instruction which causes the

contents of the saved registers to be recovered from the stack.

Note:

As a consequence of the IRET instruction, the I bit is cleared and the main program

resumes.

Priority management

By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware

entering in interrupt routine.

In the case when several interrupts are simultaneously pending, an hardware priority

defines which one will be serviced first (see the Interrupt Mapping table).

Interrupts and low power mode

All interrupts allow the processor to leave the WAIT low power mode. Only external and

specifically mentioned interrupts allow the processor to leave the HALT low power mode

(refer to the “Exit from HALT” column in the Interrupt Mapping table).

7.1

Non maskable software interrupt

This interrupt is entered when the TRAP instruction is executed regardless of the state of

the I bit. It is serviced according to the flowchart in Figure 16.

7.2

External interrupts

External interrupt vectors can be loaded into the PC register if the corresponding external

interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the

HALT low power mode.

The external interrupt polarity is selected through the miscellaneous register or interrupt

ST7FOXU0 Datasheet(PDF) 42 Page - STMicroelectronics

ST7FOXU0 Datasheet(HTML) 42 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL