ST7FOXU0 datasheet(52/123 Pages) STMICROELECTRONICS

52 / 123 page

Power saving modes

ST7FOXU0

52/123

Figure 22.

Halt timing overview

A reset pulse of at least 42 µs must be applied when exiting from Halt mode.

Figure 23.

Halt mode flowchart

WDGHALT is an option bit. See option byte section for more details.

Peripheral clocked with an external clock source can still be active.

Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table : for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set

during the interrupt routine and cleared when the CC register is popped.

The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.

HALT

RUN

256 CPU CYCLE

DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

[Active Halt disabled]

HALT INSTRUCTION

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

IBIT

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

IBIT

OFF

X 4)

CPU

OSCILLATOR

PERIPHERALS

IBITS

X 4)

256 CPU CLOCK CYCLE

DELAY 5)

WATCHDOG

ENABLE

DISABLE

WDGHALT 1)

WATCHDOG

RESET

(Active Halt disabled)

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