TNETV1644ZDU6 datasheet(131/306 Pages) TI1

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TMS320DM6437

Digital Media Processor

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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

As shown in Table 3-42, the major configuration choices of the EMIFA/VPSS Block are determined by the

following PINMUX register fields:

• PINMUX1 register field PCIEN

• PINMUX0 register fields AEM, VENCSEL, CCDCSEL

Based on the peripheral needs, select from the major configuration options in this block: Major

Configuration Options A, B, C, D, E, F, and G.

The following is an example on how to read Table 3-42. For example, the "PINMUX Selection Fields"

columns indicate that Major Configuration Choice B is selected through setting PINMUX1.PCIEN = 0,

PINMUX0.AEM = 1, VENCSEL = 0 or 1 (based on the system's VPBE requirement), and CCDCSEL = 0

or 1 (based on the system's VPFE requirement). The "Resulting Peripherals/Pins" columns indicate that

Major Configuration Option B can support the following combination of pin functions:

• No PCI pins

• Pins for 8-bit EMIFA (Async or NAND) function. The number of address pins supported provide

32KByte to 16MByte address reach per EMIFA Chip Select (CS) space.

• Pins for up to 8-bit VPBE. If 8-bit VPBE (VENCSEL = 1) is selected, the user may have 0 to 4 GPIO

pins. Exact detail on number of GPIO pins and VPBE control pins is further determined by other

PINMUX0 settings discussed in the EMIFA/VPSS Sub-Block 1 Configuration Choices.

• Pins for up to 16-bit VPFE. If 8 to 16-bit VPFE (CCDCSEL = 1) is selected, the user may have 0 to 10

GPIO pins. Exact detail on number of GPIO pins and VPFE control pins is furthered determined by

other PINMUX0 settings discussed in the EMIFA/VPSS Sub-Block 0 Configuration Choices.

After using Table 3-42 to select the Major Configuration Option for the EMIFA/VPSS Block, proceed to

select the detailed pin choices in the EMIFA/VPSS Sub-Blocks.

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Device Configurations

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TNETV1644ZDU6 Datasheet(PDF) 131 Page - Texas Instruments