TNETV1644ZDU6 datasheet(104/306 Pages) TI1

104 / 306 page

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 3-19. PINMUX0 Register Descriptions (continued)

Bit

Field Name

Description

Pins Controlled

8-bit EMIFA (Async) Pinout Mode 1 Address Width Select or Fast Boot PLL

Multiplier Select

This field serves two purposes:

If AEM = 001b, this field serves as the 8-bit EMIFA (Async) Pinout Mode 1

Address Width Select.

If FASTBOOT = 1 and AEM = 0 (000b), 3 (011b), 4 (100b), or 5 (101b), this

field serves as the Fastboot PLL Multiplier Select.

Fastboot PLL Multiplier Select: For more details on the AEAW pin functions as

Fastboot PLL Multiplier Select, see Section 3.4.1, Bootmodes.

EMIFA Address Width Select:

Sub-Block 0

000b = EMIFA (Async) pinout supports only EM_A[12:0] address pins.

EMIFA (Async) signals EM_A[20:13] are not pinned out. PINMUX bit fields

CI7(CCD15)/EM_A[13]/AD25/EM_D[0]/GP[51]

PCIEN, CI76SEL, CI54SEL, CI32SEL, and CI10SEL determine the function of

CI6(CCD14)/EM_A[14]/AD27/EM_D[1]/GP[50]

these 8 pins.

CI5(CCD13)/EM_A[15]/AD29/EM_D[2]/GP[49]

CI4(CCD12)/EM_A[16]/PGNT/EM_D[3]/GP[48]

001b = EMIFA (Async) pinout supports only EM_A[14:0] address pins.

CI3(CCD11)/EM_A[17]/AD31/EM_D[4]/GP[47]

EMIFA (Async) signals EM_A[14:13] are pinned out. PINMUX0 bit field CI76SEL

18:16

AEAW(2)

CI2(CCD10)/EM_A[18]/PRST/EM_D[5]/GP[46]

must be programmed to 0.

CI1(CCD9)/EM_A[19]/PREQ/EM_D[6]/GP[45]

EMIFA (Async) signals EM_A[20:15] are not pinned out. PINMUX0 bit fields

CI0(CCD8)/EM_A[20]/PINTA/EM_D[7]/GP[44]

CI54SEL, CI32SEL, and CI10SEL determine the function of these 6 pins.

The combination of PINMUX0/1 fields PCIEN,

010b = EMIFA (Async) pinout supports only address pins EM_A[16:0].

AEM, AEAW, CI10SEL, CI32SEL, CI54SEL,

EMIFA (Async) signals EM_A[16:13] are pinned out. PINMUX0 bit fields CI76SEL

and CI76SEL control the muxing of these 8

and CI54SEL must be programmed to 0.

pins. (1)

EMIFA (Async) signals EM_A[20:17] are not pinned out. PINMUX0 bit fields

CI32SEL and CI10SEL determine the function of these 4 pins.

011b = EMIFA (Async) pinout supports only address pins EM_A[18:0].

EMIFA (Async) signals EM_A[18:13] are pinned out. PINMUX0 bit fields

CI76SEL, CI54SEL, and CI32SEL must be programmed to 0.

EMIFA (Async) signals EM_A[20:19] are not pinned out. PINMUX0 bit field

CI10SEL determines the function of these 2 pins.

100b = EMIFA (Async) pinout supports address pins EM_A[20:0].

EMIFA (Async) signals EM_A[20:13] are pinned out. PINMUX0 bit fields

CI76SEL, CI54SEL, CI32SEL, and CI10SEL must be programmed to 0.

101b through 111b = Reserved.

VPBE Clock Select.

Sub-Block 1

0 = GPIO (default)

VPBECLK/GP[30]

VPBECKEN

Pin functions as GPIO (GP[30]).

The PINMUX0 field VPBECKEN alone controls

1 = VPBE Clock (VPBECLK)

the muxing of this pin.

Pin functions as VPBE Clock (VPBECLK).

VENC RGB Mode and LCD_FIELD Select.

000b = No VENC RGB Mode or LCD_FIELD supported.

These pins function as GPIO and/or EMIFA based on AEM setting (default).

001b = LCD_FIELD Mode.

Sub-Block 1

VENC LCD_FIELD pin function is supported. The remaining 7 pins function as

GPIO and/or EMIFA based on AEM setting.

G0/EM_CS2/GP[12]

Applicable only if AEM = 0 (000b), 4 (100b), or 5 (101b).

B0/LCD_FIELD/EM_A[3]/GP[11]

R0/EM_A[4]/GP[10]/(AEAW2/PLLMS2)

010b = RGB666 Mode.

G1/EM_A[1]/(ALE)/GP[9]/AEAW1/PLLMS1)

VENC RGB666 pins (R2, B2) are supported, along with 6 GPIO pins (GP[12:7]).

14:12

RGBSEL

B1/EM_A[2]/(CLE)/GP[8]/(AEAW0/PLLMS0)

Applicable only if AEM = 0 (000b).

R1/EM_A[0]/GP[7]/(AEM2)

R2/EM_BA[0]/GP[6]/(AEM1)

011b = RGB666 + LCD_FIELD Mode.

B2/EM_BA[1]/GP[5]/(AEM0)

VENC RGB666 (R2, B2) and LCD_FIELD pins are supported, along with 5 GPIO

pins (GP[12] and GP[10:7]).

The combination of PINMUX0 fields RGBSEL

Applicable only if AEM = 0 (000b).

and AEM, control the muxing of these 8 pins. (1)

100b = RGB888 Mode.

VENC RGB888 (G0, B0, R0, G1, B1, R1, R2, B2) pins are supported.

Applicable only if AEM = 0 (000b).

101b through 111b = Reserved.

(2)

The AEAW default value is latched at reset from AEAW[2:0] configuration inputs. The latched values are also shown at

BOOTCFG.PLLMS (read-only).

Device Configurations

104

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