TNETV1644ZDU6 datasheet(270/306 Pages) TI1

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6.17 Ethernet Media Access Controller (EMAC)

6.17.1

EMAC Peripheral Register Description(s)

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

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The Ethernet Media Access Controller (EMAC) provides an efficient interface between DM6437 and the

network. The DM6437 EMAC supports both 10Base-T (10 Mbits/second [Mbps]) and 100Base-TX (100

Mbps) in either half- or full-duplex mode. The EMAC module also supports hardware flow control and

quality of service (QOS) support.

The EMAC controls the flow of packet data from the DM6437 device to the PHY. The MDIO module

controls PHY configuration and status monitoring.

The EMAC module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple

Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE

802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).

Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER.

Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will

intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame

will be detected as an error by the network.

Both the EMAC and the MDIO modules interface to the DM6437 device through a custom interface that

allows efficient data transmission and reception. This custom interface is referred to as the EMAC control

module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to

multiplex and control interrupts.

For the DM6437 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

Module User's Guide (literature number SPRU941) which describes the DM6437 EMAC peripheral in

detail, see Section 2.9, Documentation Support section . For a list of supported registers and register

fields, see Table 6-81 [Ethernet MAC (EMAC) Control Registers] and Table 6-82 [EMAC Statistics

Registers] in this data manual.

Table 6-81. Ethernet MAC (EMAC) Control Registers

HEX ADDRESS RANGE

ACRONYM

01C8 0000

TXIDVER

Transmit Identification and Version Register

01C8 0004

TXCONTROL

Transmit Control Register

01C8 0008

TXTEARDOWN

Transmit Teardown Register

01C8 0010

RXIDVER

Receive Identification and Version Register

01C8 0014

RXCONTROL

Receive Control Register

01C8 0018

RXTEARDOWN

Receive Teardown Register

01C8 0080

TXINTSTATRAW

Transmit Interrupt Status (Unmasked) Register

01C8 0084

TXINTSTATMASKED

Transmit Interrupt Status (Masked) Register

01C8 0088

TXINTMASKSET

Transmit Interrupt Mask Set Register

01C8 008C

TXINTMASKCLEAR

Transmit Interrupt Mask Clear Register

01C8 0090

MACINVECTOR

MAC Input Vector Register

01C8 00A0

RXINTSTATRAW

Receive Interrupt Status (Unmasked) Register

01C8 00A4

RXINTSTATMASKED

Receive Interrupt Status (Masked) Register

01C8 00A8

RXINTMASKSET

Receive Interrupt Mask Set Register

01C8 00AC

RXINTMASKCLEAR

Receive Interrupt Mask Clear Register

01C8 00B0

MACINTSTATRAW

MAC Interrupt Status (Unmasked) Register

01C8 00B4

MACINTSTATMASKED

MAC Interrupt Status (Masked) Register

01C8 00B8

MACINTMASKSET

MAC Interrupt Mask Set Register

01C8 00BC

MACINTMASKCLEAR

MAC Interrupt Mask Clear Register

01C8 0100

RXMBPENABLE

Receive Multicast/Broadcast/Promiscuous Channel Enable Register

01C8 0104

RXUNICASTSET

Receive Unicast Enable Set Register

Peripheral Information and Electrical Specifications

270

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