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6.13 Host-Port Interface (HPI) Peripheral

6.13.1 HPI Device-Specific Information

6.13.2 HPI Peripheral Register Description(s)

TMS320DM6437

Digital Media Processor

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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

The DM6437 device includes a user-configurable 16-bit Host-port interface (HPI16).

Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the

DM6437.

The DM6437 HPI does not support the HAS feature. For proper device operation, the HAS pin must be

pulled up via an external resistor.

Table 6-55. HPI Control Registers

HEX ADDRESS RANGE

ACRONYM

COMMENTS

01C6 7800

PID

Peripheral Identification Register

The CPU has read/write

01C6 7804

PWREMU_MGMT

HPI power and emulation management register

access to the

PWREMU_MGMT register.

01C6 7808 - 01C6 7824

Reserved

01C6 7828

Reserved

01C6 782C

Reserved

The Host and the CPU both

01C6 7830

HPIC

HPI control register

have read/write access to the

HPIC register.

HPIA

HPI address register

The Host has read/write

01C6 7834

(HPIAW)(1)

(Write)

access to the HPIA registers.

The CPU has only read

HPIA

HPI address register

01C6 7838

access to the HPIA registers.

(HPIAR)(1)

(Read)

01C6 780C - 01C6 7FFF

Reserved

(1)

There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that

HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the

perspective of the Host. The CPU can access HPIAW and HPIAR independently. For more details about the HPIA registers and their

modes, see the TMS320DM643x DMP Host Port Interface (HPI) User's Guide (literature number SPRU998).

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