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6.4.1

EDMA3 Channel Synchronization Events

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.

Table 6-6 lists the source of EDMA synchronization events associated with each of the programmable

EDMA channels. For the DM6437 device, the association of an event to a channel is fixed; each of the

EDMA channels has one specific event associated with it. These specific events are captured in the

EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers

(EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled,

captured, processed, linked, chained, and cleared, etc., see the TMS320DM643x DMP Enhanced Direct

Memory Access (EDMA3) Controller User’s Guide (literature number SPRU987).

Table 6-6. DM6437 EDMA Channel Synchronization Events(1)

EDMA

EVENT NAME

EVENT DESCRIPTION

CHANNEL

0-1

–

Reserved

XEVT0

McBSP0 Transmit Event

REVT0

McBSP0 Receive Event

XEVT1

McBSP1 Transmit Event

REVT1

McBSP1 Receive Event

HISTEVT

VPSS Histogram Event

H3AEVT

VPSS H3A Event

PRVUEVT

VPSS Previewer Event

RSZEVT

VPSS Resizer Event

AXEVTE0

McASP0 Transmit Event Even

AXEVTO0

McASP0 Transmit Event Odd

AXEVT0

McASP0 Transmit Event

AREVTE0

McASP0 Receive Event Even

AREVTO0

McASP0 Receive Event Odd

AREVT0

McASP0 Receive Event

16-21

–

Reserved

URXEVT0

UART 0 Receive Event

UTXEVT0

UART 0 Transmit Event

URXEVT1

UART 1 Receive Event

UTXEVT1

UART 1 Transmit Event

–

Reserved

–

Reserved

ICREVT

I2C Receive Event

ICXEVT

I2C Transmit Event

30-31

–

Reserved

GPINT0

GPIO 0 Interrupt

GPINT1

GPIO 1 Interrupt

GPINT2

GPIO 2 Interrupt

GPINT3

GPIO 3 Interrupt

GPINT4

GPIO 4 Interrupt

GPINT5

GPIO 5 Interrupt

GPINT6

GPIO 6 Interrupt

GPINT7

GPIO 7 Interrupt

GPBNKINT0

GPIO Bank 0 Interrupt

GPBNKINT1

GPIO Bank 1 Interrupt

(1)

In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate

transfer completion events. For more detailed information on EDMA event-transfer chaining, see the Document Support section for the

Enhanced Direct Memory Access (EDMA) Controller Reference Guide.

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