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TNETV1644ZDU6 Datasheet(PDF) 166 Page - Texas Instruments |
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TNETV1644ZDU6 Datasheet(HTML) 166 Page - Texas Instruments |
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166 / 306 page ![]() DSP Subsystem SYSCLK1 SYSCLK3 SCR EDMA VPFE VPBE DACs DDR2 PHY DDR2 VTP DDR2 Mem Ctlr PLLDIV2 (/10) PLLDIV1 (/2) BPDIV PLL Controller 2 PLL Controller 1 PLLDIV2 (/3) PLLDIV3 (/6) PLLDIV1 (/1) SYSCLK2 UARTs (x2) I2C Timers (x3) PWMs (x3) EMAC EMIFA VLYNQ HPI McASP0 McBSP0 GPIO McBSP1 PCI MXI/CLKIN (27 MHz) PCLK VPBECLK OSCDIV1 (/1) HECC OBSCLK (CLKOUT0 Pin) BPDIV (/1) AUXCLK TMS320DM6437 Digital Media Processor SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com Table 6-3. PLLC1 Programming for CLKDIV1, CLKDIV3, CLKDIV6 Domains CLKDIV1 DOMAIN CLKDIV3 DOMAIN CLKDIV6 DOMAIN (SYSCLK1) (SYSCLK2) (SYSCLK3) PLL1 PLL1 PLL1 PLLDIV1.RATIO PLLDIV2.RATIO PLLDIV3.RATIO Divide-Down Divide-Down Divide-Down DIV1 /1 0 /3 2 /6 5 DIV2 /2 1 /6 5 /12 11 DIV3 /3 2 /9 8 /18 17 Figure 6-4. PLL1 and PLL2 Clock Domain Block Diagram For further detail on PLL1 and PLL2, see the structure block diagrams Figure 6-5 and Figure 6-6, respectively. Peripheral Information and Electrical Specifications 166 Submit Documentation Feedback |
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