TNETV2664FIBZWT datasheet(135/249 Pages) TI1

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PLLDIV1(/1)

PLLDIV3(/6)

PLLDIV2(/3)

SYSCLK1

(CLKDIV1Domain)

SYSCLK3

(CLKDIV6Domain)

SYSCLK2

(CLKDIV3Domain)

PLLM

PLL

CLKMODE

CLKIN

OSCIN

PLLEN

AUXCLK

(CLKINDomain)

OSCDIV1

OBSCLK

(CLKOUT0Pin)

PLLOUT

PLLDIV1 (/2)

PLLM

PLL

BPDIV

CLKMODE

CLKIN

OSCIN

PLLEN

PLL2_SYSCLK1

(DDR2 PHY)

PLL2_SYSCLKBP

(DDR2 VTP)

PLLOUT

TMS320C6424

www.ti.com

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Figure 6-5. PLL1 Structure Block Diagram

Figure 6-6. PLL2 Structure Block Diagram

6.3.5

Power and Sleep Controller (PSC)

The Power and Sleep Controller (PSC) controls power by turning off unused power domains or by gating

off clocks to individual peripherals/modules. The C6424 device only utilizes the clock gating feature of the

PSC for power savings. The PSC consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs).

The GPSC contains memory mapped registers, PSC interrupt control, and a state machine for each

peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset

control. The LPSCs for C6424 are shown in Table 6-4. The PSC Register memory map is given in

Table 6-5. For more details on the PSC, see the TMS320C642x Power and Sleep Controller (PSC)

Reference Guide (literature number SPRUEN8).

Peripheral Information and Electrical Specifications

135

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