TNETV2664FIBZWT datasheet(150/249 Pages) TI1

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TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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Table 6-8. EDMA Parameter Set RAM

HEX ADDRESS RANGE

DESCRIPTION

0x01C0 4000 - 0x01C0 401F

Parameters Set 0 (8 32-bit words)

0x01C0 4020 - 0x01C0 403F

Parameters Set 1 (8 32-bit words)

0x01C0 4040 - 0x01C0 405F

Parameters Set 2 (8 32-bit words)

0x01C0 4060 - 0x01C0 407F

Parameters Set 3 (8 32-bit words)

0x01C0 4080 - 0x01C0 409F

Parameters Set 4 (8 32-bit words)

0x01C0 40A0 - 0x01C0 40BF

Parameters Set 5 (8 32-bit words)

...

0x01C0 4FC0 - 0x01C0 4FDF

Parameters Set 126 (8 32-bit words)

0x01C0 4FE0 - 0x01C0 4FFF

Parameters Set 127 (8 32-bit words)

Table 6-9. Parameter Set Entries

HEX OFFSET ADDRESS

ACRONYM

PARAMETER ENTRY

WITHIN THE PARAMETER SET

0x0000

OPT

Option

0x0004

SRC

Source Address

0x0008

A_B_CNT

A Count, B Count

0x000C

DST

Destination Address

0x0010

SRC_DST_BIDX

Source B Index, Destination B Index

0x0014

LINK_BCNTRLD

Link Address, B Count Reload

0x0018

SRC_DST_CIDX

Source C Index, Destination C Index

0x001C

CCNT

C Count

6.5

Reset

The reset controller detects the different type of resets supported on the C6424 device and manages the

distribution of those resets throughout the device.

The C6424 device has several types of device-level resets - power-on reset, warm reset, max reset, and

CPU reset. Table 6-10 explains further the types of reset, the reset initiator, and the effects of each reset

on the chip. See Section 6.5.9, Reset Electrical Data/Timing, for more information on the effects of each

reset on the PLL controllers and their clocks.

Table 6-10. Device-Level Global Reset Types

TYPE

INITIATOR

EFFECT(s)

Global chip reset (Cold reset). Activates the POR signal on chip,

which resets the entire chip including the emulation logic.

Power-on Reset

POR pin

The power-on reset (POR) pin must be driven low during power

(POR)

ramp of the device.

Device boot and configuration pins are latched.

Resets everything except for the emulation logic. Emulator stays

Warm Reset

RESET pin

alive during Warm Reset.

Device boot and configuration pins are latched.

Same as a Warm Reset, except the C6424 device boot and

Max Reset

Emulator, WD Timer (Timer 2)

configuration pins are not re-latched.

In addition to device-level global resets, the PSC provides the capability to cause local resets to

peripherals and/or the CPU.

6.5.1

Power-on Reset (POR Pin)

Power-on Reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the

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Peripheral Information and Electrical Specifications

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