REV. 0

AD9821

–13–

CMOS

OR

CCD

IMAGER

VIN+

BUFFER

OR

LEVEL SHIFT

OUT+

AD9821

REGISTER-

DATA

SERIAL

INTERFACE

DIGITAL

OUTPUTS

DIGITAL IMAGE

PROCESSING

ASIC

(MAY ALSO

INCLUDE TG)

TIMING

GENERATOR

V-DRIVE

(CCD)

IMAGER

TIMING

DATACLK/CLAMP

TIMING

VIN–

OUT–

Figure 12. System Applications Diagram

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

37

48 47 46 45 44

39 38

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

TEST

AVSS

TEST

AVDD2

BYP1

VIN-

VIN+

TEST

TEST

AVDD1

AVSS

AVSS

D0

D1

D2

D3

D4

D5

D6

D7

D8

(MSB) D11

AD9821

3V

ANALOG SUPPLY

IMAGER INPUT, POSITIVE

3V

ANALOG SUPPLY

12

DATA

OUTPUTS

3

SERIAL

INTERFACE

0.1 F

3V

ANALOG SUPPLY

3

CLOCK

INPUTS

3V

ANALOG SUPPLY

3V

DRIVER

SUPPLY

NC = INTERNALLY NOT CONNECTED

D9

D10

IMAGER INPUT, NEGATIVE/REFERENCE

1.0 F

1.0 F

0.1 F

0.1 F

0.1 F

0.1 F

0.1 F

Figure 13. Recommended Circuit Configuration

APPLICATIONS INFORMATION

The AD9821 is a complete Analog Front End (AFE) product

for a variety of imager applications using CMOS image sensors

and CCDs with on-chip CDS. As shown in Figure 10, the imager

output is generally buffered and sent to the AD9821’s analog

inputs, either as a differential or single-ended signal. The AD9821

performs the sample-and-hold operation, gain adjustment,

black level correction, and analog-to-digital conversion. The

AD9821’s digital output data is then processed by the image

processing ASIC. The internal registers of the AD9821—used

to control gain, offset level, and other functions—are

programmed by the ASIC or microprocessor through a 3-wire

serial digital interface. A system timing generator provides the

clock signals for both the imager and the AFE.