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AD5675

Data Sheet

Rev. B | Page 20 of 26

WRITE AND UPDATE COMMANDS

Write to Input Register n (Dependent on LDAC)

Command 0001 allows the user to write to the dedicated input

Update DAC Register n with Contents of Input Register n

Command 0010 loads the DAC registers and outputs with the

contents of the selected input registers and updates the DAC

outputs directly.

Write to and Update DAC Channel n (Independent of LDAC)

Command 0011 allows the user to write to the DAC registers

and updates the DAC outputs directly.

I2C SLAVE ADDRESS

The AD5675 has a 7-bit I2C slave address. The five MSBs are

00011, and the two LSBs (A1 and A0) are set by the state of the

A1 and A0 address pins. The ability to make hardwired changes to

A1 and A0 allows the user to incorporate up to four AD5675

devices on one bus (see Table 11).

Table 11. Device Address Selection

A1 Pin Connection

A0 Pin Connection

GND

VLOGIC

GND

VLOGIC

SERIAL OPERATION

The 2-wire I2C serial bus protocol operates as follows:

The master initiates a data transfer by establishing a start

condition when a high to low transition on the SDA line

occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address.

The slave device with the transmitted address responds by

pulling SDA low during the ninth clock pulse (this is called

the acknowledge bit, or ACK). At this stage, all other

devices on the bus remain idle while the selected device waits

for data to be written to or read from its input shift register.

Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

Transitions on the SDA line must occur during the low period

of SCL; SDA must remain stable during the high period of SCL.

After all data bits are read or written, a stop condition is

established. In write mode, the master pulls the SDA line high

during the 10th clock pulse to establish a stop condition. In

read mode, the master issues a no acknowledge (NACK)

for the ninth clock pulse (that is, the SDA line remains

high). The master then brings the SDA line low before the

10th clock pulse, and then high again during the 10th clock

pulse to establish a stop condition.

WRITE OPERATION

When writing to the AD5675, begin with a start command

followed by an address byte (R/W = 0), after which the DAC

acknowledges that it is prepared to receive data by pulling SDA

low. The AD5675 require two bytes of data for the DAC, and a

command byte that controls various DAC functions. Three bytes

of data must, therefore, be written to the DAC with the command

byte followed by the most significant data byte and the least

significant data byte, as shown in Figure 43. All these data bytes

are acknowledged by the AD5675. A stop condition follows.

FRAME 2

COMMAND BYTE

FRAME 1

SLAVE ADDRESS

SCL

START BY

MASTER

ACK BY

AD5675

ACK BY

AD5675

SDA

R/W

DB23

DB22 DB21 DB20 DB19 DB18 DB17 DB16

ACK BY

AD5675

ACK BY

AD5675

FRAME 4

LEAST SIGNIFICANT

DATA BYTE

FRAME 3

MOST SIGNIFICANT

DATA BYTE

STOP BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Figure 43. I2C Write Operation

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