P9038 DATASHEET

P9038 August 1, 2016

5

©2016 Integrated Device Technology, Inc.

NOTES:

1. 10m

 1% or better sense resistor is required to meet the FOD specification

2. This current is the sum of the input currents for REG_IN, IN, ISNSP_IN, ISNSN_IN, and EN_B.

3. 3.For internal use - do not externally load.

4. Guaranteed by Design.

5. Any of the GPIO pins is capable of sourcing 8mA. The GPIO connected to the ADC have a max operating input voltage of 2.4V to prevent saturation of the ADC.

VDP/DM_LGCLO Logic Low

0.8

V

RDP_DWN

Pull-down Resistance

14.25

19.5

24.8

k



CI

Input Capacitance

Dm pin, Switch Open

4.5

5

pF

Dp pin, Switch Open

4.5

5

pF

IILK

Input Leakage

Dm pin, Switch Open V = 5.0

-1

+1

μA

Dp pin, Switch Open V = 5.0

-1+1

μA

Clock Frequency

P9038 as Slave

0

400

kHz

Hold Time (Repeated)

for START Condition

0.6

µs

Data Hold Time

10

ns

Clock Low Period

1.3

µs

Clock High Period

0.6

µs

Set-up Time for

Repeated START

Condition

100

ns

Bus Free Time between

STOP and START

Condition

1.3

µs

Capacitive Load for

each Bus Line

100

pF

SCL, SDA

5pF

Input Threshold Low

0.4

V

Input Threshold High

1.4

V

Input Leakage Current

V = 0V & 5V

-1.0

1.0

µA

Output Logic Low (SDA) I = 2mA

0.25

V

Symbol

Description

Conditions

Min

Typ

Max

Units