LM2650 datasheet(2/11 Pages) NSC

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Connection Diagram

Pin Descriptions (Refer to the Block Diagrams)

Pins

Description

1, 12

SUB: These pins make electrical contact with the substrate of the die. Ground them. For best thermal

performance, ground them to the same large, uninterrupted copper plane as the PGND pins.

SLEEP LOGIC: Use this logic input to select the conversion mode; low selects PWM, high selects sleep, and

high impedance (open) permits the LM2650 to move freely and automatically between the modes, using PWM

for moderate to heavy loads and sleep for light loads.

3, 4, 9, 10

PGND: The ground return of the power stage. The power stage consists of the two power switches Q1 and

Q2, the gate drivers DH and DL, and the linear voltage regulators VRegH and VRegL. For best electrical and

thermal performance, ground these pins to a large, uninterrupted copper plane.

5, 8

SW: The output node of the power stage. It swings from slightly below ground to slightly below the voltage to

IN. To minimize the effects of switching noise on nearby circuitry, keep all traces originating from SW short

and to the point. Route all traces carrying signals well away from the SW traces.

6, 7

IN: The positive supply rail of the power stage. Bypass each PVIN pin to PGND with a 0.1 µF capacitor. Use

capacitors having low ESL and low ESR, and locate them close to the IC.

BOOT: The positive supply rail of the high-side gate driver DH. Connect a 0.1 µF capacitor from this node to

SW. Bootstrapping action creates a supply rail about 9V above that at PV

IN, and DH uses this rail to override

the gate of the NMOS power FET Q1. Overriding ensures low R

DS(on).

FB: The feedback input.

DD: An internal regulator steps the input voltage down to a 4V rail used by the signal-level circuitry. VDD is the

output node of this regulator. Bypass V

DD to GND close to the IC with a 0.2 µF capacitor.

COMP: The inverting input of the error amplifier EA.

EA OUT: The output node of the error amplifier EA.

SS: The soft start node. Connect a capacitor from SS to GND.

GND: The ground return of the signal-level circuitry.

IN: The positive supply rail of the internal 4V regulator. Bypass VIN to GND close to the IC with a 0.1 µF

capacitor.

FREQ ADJ: The LM2650 switches at a nominal 90 kHz. Connect a resistor between FREQ ADJ and GND to

adjust the frequency up from the nominal. Use the graph under Typical performance Characteristics to select

the resistor.

SYNC: The synchronization input. If the switching frequency is to be synchronized with an external clock

signal, apply the clock signal here. Ground if not used.

SD: Use this logic input to control shutdown; pull low for operation, high for shutdown.

SLEEP OUT ADJ (SOA): The value of the resistor connected between SIA and ground programs the sleep-in

threshold. Higher values program lower thresholds.

SLEEP IN ADJ (SIA): The value of the resistor connected between SIA and ground programs the sleep-in

threshold. Higher values program lower thresholds.

DS012848-14

Top View

24-Lead Small Outline Package (M)

Order Number LM2650M-ADJ

See Package Number M24B

LM2650 Datasheet(PDF) 2 Page - National Semiconductor (TI)

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