LM2650 datasheet(4/11 Pages) NSC

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Electrical Characteristics (Continued)

PVIN = 15V, VSLEEP LOGIC = 0V and VSD = 0V unless superseded under Conditions. Typicals and limits appearing in plain

type apply for T

A =TJ = +25˚C. Limits appearing in boldface type apply over the full junction temperature range shown under

Operating Ratings.

Symbol

Parameter

Conditions

Typ (Note 5)

Limit (Note 6)

Units

MIN

Minimum Duty Cycle

FB =VREF +50 mV,

OSC Not Adjusted

2.8

%(min)

Internal Rail Voltage

VDD =1mA

4.0

3.6/3.4

4.2/4.3

V(min)

V(max)

BOOT

Bootstrap Regulator Voltage

(VRegH)

BOOT =1mA

7.5

6.5/6.0

V(min)

Soft Start Current

13.5/20.0

µA

µA(max)

HYST

Hysteresis of the Sleep

Comparator (C2

Figure 2)

SLEEPLOGIC =3V

mV(min)

mV(max)

IL of SD

0.95

V(max)

IH of SD

2.10

V(min)

IL of SLEEP LOGIC

0.9

V(max)

IH of SLEEP LOGIC

2.0

V(min)

IL of SYNC

0.50

V(max)

IH of SYNC

1.45

V(min)

J for Thermal Shutdown

170

˚C

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which the device operates

correctly. Operating ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical

Characteristics.

Note 2: This rating is calculated using the formula PDCmax =(TJmax −TA)/ θJA, where PDCmax is the absolute maximum power dissipation, TJmax is the maximum

junction temperature, and

θJA is the junction ot ambient thermal resistance of the package. The PDCmax rating of 1.28W results from substituting 170˚C, 70˚C and

78˚C/W for TJmax,TA and θJA respectively. A θJAof 78˚C represents the worst condition of no heat sinking of the M24B small-outline package. Heat sinking allows

the safe dissipation of more power. See Application Notes on thermal management. The LM2650 actively limits its junction temperature to about 170˚C.

Note 3: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook published by National Semiconductor Corporation.

Note 4: ESD is applied using the human-body model, a 100pF capacitor discharged through a 1.5k

Ω resistor.

Note 5: A typical is the center of characterization data taken at TA =TJ = 25˚C.

Note 6: All limits are guaranteed. The guarantee is backed with 100% testing at TA =TJ = 125˚C and statistical correlation for room temperature and cold limits.

Note 7: VREF is measured at SLEEP OUT ADJ.

Note 8: Quiescent current is the total current flowing into the PVIN and VIN pins. IQ includes the current used to drive the gates of the two NMOS power FETs at the

nominal switching frequency. IQS includes no such current.

Note 9: Pulling 100µA out of FREQ ADJ simulates adjusting the oscillator frequency with a 12.5 k

Ω resistor connected from FREQ ADJ to GND. The sleep mode

cannot be used at switching frequencies above 250 kHz.

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