LE25U40CMC

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18

AC Characteristics

Parameter

Symbol

Ratings

unit

min

typ

max

Clock frequency

Read instruction(03h)

fCLK

25

MHz

All instructions except for read(03h)

40

MHz

Input signal rising/falling time

tRF

0.1

V/ns

SCK logic high level pulse width

25MHz

tCLHI

16

ns

40MHz

11.5

ns

SCK logic low level pulse width

25MHz

tCLLO

16

ns

40MHz

11.5

ns

CS setup time

tCSS

8

ns

CS hold time

tCSH

8

ns

Data setup time

tDS

2

ns

Data hold time

tDH

5

ns

CS wait pulse width

tCPH

25

ns

Output high impedance time from CS

tCHZ

8

ns

Output data time from SCK

tV

8

11

ns

Output data hold time

tHO

1

ns

Output low impedance time from SCK

tCLZ

0

ns

HOLD setup time

tHS

5

ns

HOLD hold time

tHH

3

ns

Output low impedance time from HOLD

tHLZ

9

ns

Output high impedance time from HOLD

tHHZ

9

ns

WP setup time

tWPS

20

ns

WP hold time

tWPH

20

ns

Power-down time

tDP

3

s

Power-down recovery time

tPDR

3

s

Write status register time

tSRW

5

15

ms

Page programming cycle time

tPP

4

5

ms

Small sector erase cycle time

tSSE

40

150

ms

Sector erase cycle time

tSE

80

250

ms

Chip erase cycle time

tCHE

0.25

2.0

s

AC Test Condtions

Input pulse level ··········· 0.2VDD to 0.8VDD

Input rising/falling time ·· 5ns

Input timing level ········· 0.3VDD, 0.7VDD

Output timing level ······· 1/2

VDD

Output load ················ 30pF

Note: As the test conditions for "typ", the measurements are conducted using 2.5v for VDD at room temperature.

0.8VDD

0.2VDD

0.7VDD

1/2VDD

0.3VDD

input level

input / output timing level

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be

indicated by the Electrical Characteristics if operated under different conditions.