LE25U40CMC

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11

4. Write Enable

Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is

the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command.

"Figure 8 Write Enable" shows the timing waveforms when the write enable operation is performed. The write enable

command consists only of the first bus cycle, and it is initiated by inputting (06h).

 Small sector erase, sector erase, chip erase

 Page program

 Status register write

5. Write Disable

The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 9 Write Disable"

shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by

inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable command

(06h).

Figure 8 Write Enable

Figure 9 Write Disable

6. Power-down

The power-down command sets all the commands, with the exception of the silicon ID read command and the

command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 10 Power-down" shows

the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by inputting

(B9h). However, a power-down command issued during an internal write operation will be ignored. The power-down

state is exited using the power-down exit command (power-down is exited also when one bus cycle or more of the

silicon ID read command (ABh) has been input). "Figure 11 Exiting from Power-down" shows the timing waveforms of

the power-down exit command.

Figure 10 Power-down

Figure 11 Exiting from Power-down

SCK

SI

High Impedance

SO

CS

06h

0

1

2

3

4

5

6

7

Mode3

Mode0

8CLK

SCK

SI

High Impedance

SO

CS

04h

0

1

2

3

4

5

6

7

Mode3

Mode0

8CLK

MSB

MSB

SCK

SI

High Impedance

SO

CS

B9h

0

1

2

3

4

5

6

7

Mode3

Mode0

8CLK

SCK

SI

High Impedance

SO

CS

ABh

0

1

2

3

4

5

6

7

Mode3

Mode0

8CLK

tPDR

tDP

Power down

mode

Power down

mode

MSB

MSB