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PC87591L Datasheet(PDF) 79 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de pieza PC87591L
Descripción Electrónicos  LPC Mobile Embedded Controllers
PDF  437 Pages
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Fabricante Electrónico  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87591L Datasheet(HTML) 79 Page - National Semiconductor (TI)

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4.0 Embedded Controller Modules (Continued)
Revision 1.07
79
www.national.com
4.1.7
Fast Read Bus Cycle
When FRE bit in SZCFGn register is 1, the fast read bus cycle is enabled for zone n. The fast read bus cycle takes one clock
cycle.
At the start of the T1-2 clock cycle, the address is placed on the address bus, and SELn and RD are activated. WR0-1 are
inactive, indicating a read bus cycle. At the end of the clock cycle, the BIU samples the data. SELn and RD are deactivated
in the following clock cycle, unless another read from the same zone follows. If a write to the same zone follows and late
write is configured, SELn remains activated. The address remains valid until the start of the clock cycle after the T1-2 clock
cycle.
CLK
A0-19
SELn
D0-7
RD
WR0-1
Bus State
T1
T2
T2B
In
In
BST0-2
Figure 21. Normal Read Bus Cycle with 0 Wait on Burst
CLK
A0-19
RD
WR0-1
D0-7
T1
TIW
TIW
T2
TBW
In
SELn
T2B
In
BST0-2
Figure 22. Normal Read Bus Cycle with 2 Internal Waits and 1 Wait on Burst
Bus State



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