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PC87591L Datasheet(PDF) 400 Page - National Semiconductor (TI) |
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PC87591L Datasheet(HTML) 400 Page - National Semiconductor (TI) |
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400 / 437 page  7.0 Device Specifications (Continued) www.national.com 400 Revision 1.07 7.6.11 ICU/Development Timing Figure 153. Pipe Status Signal (PFS and PLI) Timing Figure 154. Reset Out Signal Timing Symbol Figure Description Reference Conditions Min Max Unit ICU/Development Input Timing tBRKLs 153 Input setup time for BRKL Before RE CLK 10 ns tBRKLh 153 Input hold time for BRKL After RE CLK 0 ns ICU/Development Output Timing tPFSh 153 Output hold time PFS, PLI After RE CLK 0.5 * tCLK − 6ns - tPFSv 153 Output active/inactive time PFS, PLI After RE CLK 0.5 * tCLK + 12 ns - tRSTOd 154 Output delay time RSTO After RE Internal Reset 5 * tCLK - tRSTOw 154 Output pulse width RSTOFE to RE RSTO3 * tCLK - tRSTOs 154 Output inactive time RSTO Before FE Internal Reset 0 ns CLK tPFSv PFS tPFSv tPFSv PLI tPFSh tPFSv tPFSh tBRKLs t BRKLh BRKL_RSTO BRKL_RSTO Internal Reset Hi-Z Hi-Z SELIO , SEL0, SEL1 tRSTOd tRSTOw tRSTOs |
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