automatically returns to track mode, and the next eight

clock cycles shift out the result on DOUT.

A minimum of 3.5µs in track mode is required for com-

plete acquisition.

DAC Continuous Conversion Mode

Once the DAC is configured in continuous conversion

mode, the analog output, OUT, is updated at the rising

edge of every eighth clock pulse (Figure 7). To exit

DAC continuous conversion mode, toggle CS. The

device requires a new control word before any further

conversions take place.

ADC Continuous Conversion Mode

Set C0 = 1 to select continuous conversion mode. The

falling edge of SCLK after the eighth bit of the control

word causes the ADC to switch from track to hold

mode and begin conversion. To avoid corruption of the

conversion result, SCLK must be disabled for 36µs

(Figure 8). After completing the conversion, the ADC

8-Bit CODECs

______________________________________________________________________________________

13

SCLK

OUT

CS

S

DAC

ADDR

DAC OFF

S

DAC

ADDR

DAC ON

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

DIN

Figure 7. DAC Continuous Conversion Mode Timing Diagram

SCLK

AIN

DOUT

CS

SS

ADC

ADDR

ADC ON

S

ADC

ADDR

ADC ON

S

ADC

ADDR

ADC ON

ADC

ON

S ADC

ON

DIN

1

2

3

MSB LSB

CONVERSION

RESULT FOR 1

T/MIN ACQUISITION

MODE

MSB LSB

CONVERSION

RESULT FOR 2

MSB LSB

CONVERSION

RESULT FOR 3

MSB LSB

CONVERSION

RESULT FOR 4

MSB LSB

CONVERSION

RESULT FOR 5

MSB LSB

CONVERSION

RESULT FOR 6

4

5

6

7

Figure 8. ADC Continuous Conversion Mode Timing Diagram

OUTPUT CODE

FULL-SCALE

TRANSITION

11111111

11111110

11111101

00000011

00000010

00000001

00000000

0.5 1.5 2.5

0

FS

FS - 1.5LSB

INPUT VOLTAGE (LSB)

(IN-)

Figure 9. ADC Input/Output Transfer Function