TMS570LS0232PZ datasheet(72/109 Pages) TI1

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TMS570LS0232

SPNS242A – OCTOBER 2014 – REVISED JUNE 2015

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Table 7-6. MibADC Timing Specifications

PARAMETER

MIN

NOM

MAX

UNIT

tc(ADCLK)

(1)

Cycle time, MibADC clock

td(SH)

(2)

Delay time, sample and hold time

200

Delay time from ADC power on until first input can be

td(PU-ADV)

µs

sampled

12-BIT MODE

td(C)

Delay time, conversion time

400

td(SHC)

(3)

Delay time, total sample/hold and conversion time

600

10-BIT MODE

td(C)

Delay time, conversion time

330

td(SHC)

(3)

Delay time, total sample/hold and conversion time

530

(1)

The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits

4:0.

(2)

The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each

conversion group. The sample time must be determined by accounting for the external impedance connected to the input channel as

well as the internal impedance of the ADC.

(3)

This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors for

example, the prescale settings.

Peripheral Information and Electrical Specifications

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