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P4C1024-15P3C Datasheet(PDF) 5 Page - Pyramid Semiconductor Corporation |
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P4C1024-15P3C Datasheet(HTML) 5 Page - Pyramid Semiconductor Corporation |
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5 / 8 page ![]() P4C1024 Page 5 of 14 Document # SRAM124 REV A TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CE CE CE CE 1, CE2 CONTROLLED) (5,7,10) Notes: 9. READ Cycle Time is measured from the last valid address to the first transitioning address. 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE 1 or CE2 causes them. |
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