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DP83902AVLC Datasheet(PDF) 62 Page - National Semiconductor (TI) |
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DP83902AVLC Datasheet(HTML) 62 Page - National Semiconductor (TI) |
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62 / 70 page ![]() 150 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) Remote DMA (Read Send Command) Recovery Time TLF11157 – 43 Symbol Parameter Min Max Units bpwrl Bus Clock to Port Write Low 43 ns bpwrh Bus Clock to Port Write High 40 ns prqh Port Write High to Port Request High (Note 1) 30 ns prql Port Request Low from Read Acknowledge High 60 ns rakw Remote Acknowledge Read Strobe Pulse Width 20 ns rhpwh Read Acknowledge High to Next Port Write Cycle 11 BSCK (Notes 2 3 4) Note 1 Start of next transfer is dependent on where RACK is generated relative to BSCK and whether or not a local DMA is pending Note 2 This is not a measured value but guaranteed by design Note 3 RACK must be high for a minimum of 7 BSCK Note 4 Assumes no local DMA interleave no CS and immediate BACK 62 |
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